參數(shù)資料
型號： MC68HC05LJ5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 31/81頁
文件大?。?/td> 905K
代理商： MC68HC05LJ5P
November 10, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05LJ5
LOW POWER MODES
MOTOROLA
REV 1
6-3
6.1.2 HALT Mode
Execution of the STOP instruction in this mode (as chosen by a mask option)
places the MCU in a low-power mode, which consumes more power than the
STOP Mode. In the HALT Mode the internal processor clock is halted, suspending
all processor and internal bus activity. Internal timer clocks remain active, permit-
ting interrupts to be generated from the timer or a reset to be generated from the
COP Watchdog Timer. Execution of the STOP instruction automatically clears the
I-bit in the Condition Code Register and sets the IRQE enable bit in the IRQ Con-
trol/Status Register so that the IRQ external interrupt is enabled. All other regis-
ters, memory, and input/output lines remain in their previous states.
The HALT Mode may be exited when a Timer interrupt, an external IRQ, an LVR
reset, or external RESET occurs. When exiting the HALT Mode the internal pro-
cessor clock will resume after a delay of one to 4064 internal processor clock
cycles. This varied delay time is due to the HALT Mode testing the oscillator stabi-
lization delay timer (a feature of the STOP Mode) which has been free-running (a
feature of the WAIT Mode).
NOTE
The HALT Mode is not intended for normal use, but is provided to keep the COP
Watchdog Timer active should the STOP instruction opcode be inadvertently
executed.
6.2
WAIT MODE
The WAIT instruction places the MCU in a low-power mode, which consumes
more power than the STOP Mode. In the WAIT Mode the internal processor clock
is halted, suspending all processor and internal bus activity. Internal timer clocks
remain active, permitting interrupts to be generated from the timer or a reset to be
generated from the COP Watchdog Timer. Execution of the WAIT instruction auto-
matically clears the I-bit in the Condition Code Register and sets the IRQE enable
bit in the IRQ Control/Status Register so that the IRQ external interrupt is enabled.
All other registers, memory, and input/output lines remain in their previous states.
If timer interrupts are enabled, a TIMER interrupt will cause the processor to exit
the WAIT Mode and resume normal operation. The Timer may be used to gener-
ate a periodic exit from the WAIT Mode. The WAIT Mode may also be exited when
an external IRQ or an LVR reset or an external RESET occurs.
6.3
DATA-RETENTION MODE
If the LVR mask option is selected and since LVR kicks in whenever VDD is below
the specied LVR trigger voltage which is higher than that required of the Data
Retention mode, the Data Retention mode will not exist. Data Retention Mode is
only meaningful if LVR mask option is not selected.
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