參數(shù)資料
型號： MC68HC05LJ5P
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16
封裝： PLASTIC, DIP-16
文件頁數(shù)： 28/81頁
文件大?。?/td> 905K
代理商： MC68HC05LJ5P
GENERAL RELEASE SPECIFICATION
November 10, 1998
MOTOROLA
RESETS
MC68HC05LJ5
5-2
REV 1
The POR will generate the RST signal which will reset the CPU. If any other reset
function is active at the end of this 4064 cycle delay, the RST signal will remain in
the reset condition until the other reset condition(s) end.
5.2.2 Computer Operating Properly Reset (COPR)
The internal COPR reset is generated automatically (if the COP is enabled) by a
time-out of the COP Watchdog Timer. This time-out occurs if the counter in the
COP Watchdog Timer is not reset (cleared) within a specic time by a software
reset sequence. The COP Watchdog Timer can be disabled by a mask option.
Refer to Section 8.2 for more information on this time-out feature. COP reset also
forces the RESET pin low
The COPR will generate the RST signal which will reset the CPU and other
peripherals. Also, the COPR will establish the mode of operation based on the
state of the IRQ pin at the time the COPR signal ends. If the voltage on the IRQ
pin is at the VTST level, the state of the PB0 pin during the last rising edge of the
RESET pin will determine which Test Mode (Internal or Expanded) the MCU will
be in. If the voltage at the IRQ pin is in the normal operating range (VSS to VDD),
the MCU will enter Single-Chip Mode when the COPR signal ends. If any other
reset function is active at the end of the COPR reset signal, the RST signal will
remain in the reset condition until the other reset condition(s) end.
5.2.3 Low Voltage Reset (LVR)
The internal LVR reset is generated when VDD falls below the specied LVR trig-
ger value VLVR for at least one tCYC. In typical applications, the power supply
decoupling circuit will eliminate negative-going voltage glitches of less than one
tCYC. This reset will hold the MCU in the reset state until VDD rises above VLVR.
Whenever VDD is above VLVR and below 4.5V, the MCU is guaranteed to operate
although not within specication. The output from the LVR is connected directly to
the internal reset circuitry and also forces the RESET pin low. The internal reset
will be removed once the power supply voltage rises above VLVR, at which time a
normal power-on-reset sequence occurs.
5.2.4 Illegal Address Reset (ILADR)
The internal ILADR reset is generated when an instruction opcode fetch occurs
from an address which is not implemented in the RAM ($00C0 - $00FF) nor ROM
($0300-$07FF). The ILADR will generate the RST signal which will reset the CPU
and other peripherals. If any other reset function is active at the end of the ILADR
reset signal, the RST signal will remain in the reset condition until the other reset
condition(s) end. Notice that ILADR also forces the RESET pin low
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