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參數(shù)資料
| 型號： | MC68HC05LJ5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 35/81頁 |
| 文件大小： | 905K |
| 代理商： | MC68HC05LJ5P |
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GENERAL RELEASE SPECIFICATION
November 10, 1998
MOTOROLA
INPUT/OUTPUT PORTS
MC68HC05LJ5
7-2
REV 1
Data Direction Register (DDRA) is located at address $0004. The Port A Pull-
down/up Register (PDURA) is located at address $0010. Reset clears the DDRA
and the PDURA. The Port A Data Register is unaffected by reset.
Figure 7-2. Port A I/O Circuitry
7.2.1 Port A Data Register
Each Port A I/O pin has a corresponding bit in the Port A Data Register. When a
Port A pin is programmed as an output the state of the corresponding data regis-
ter bit determines the state of the output pin. When a Port A pin is programmed as
an input, any read of the Port A Data Register will return the logic state of the cor-
responding I/O pin. The Port A data register is unaffected by reset.
7.2.2 Port A Data Direction Register
Each Port A I/O pin may be programmed as an input by clearing the correspond-
ing bit in the DDRA, or programmed as an output by setting the corresponding bit
in the DDRA. The DDRA can be accessed at address $0004. The DDRA is
cleared by reset.
If congured as output pins, PA6 and PA7 have slow output falling-edge transition
feature. The slow transition feature is controlled by the SLOWE bit of DDRB.
SLOWE bit, if set and if the pin is congured as an output pin, enables the slow
falling-edge output transition feature of all three I/O lines, PA6, PA7, and PB1.
Write $0010
Read $0000
Write $0000
Read $0004
Write $0004
Internal HC05
Data Bus
100
A
Pull-down
Data
Register Bit
Output
Mask Option
(Software Pull-down/up Inhibit)
Reset
(RST)
Data Direction
Register Bit
Pulldown/up
Register Bit
VDD
5K
Pull-up
Note: Each I/O port pin can have either pull-up or pull-down device, but not both.
PA6 and PA7 output drivers are of open-drain type
I/O Pin
8 mA Sink
Capability
(Bits 4-7 Only)
PA0-PA3 and PA7 only:
to IRQ interrupt system
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