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參數(shù)資料
| 型號： | MC68HC05LJ5P |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁數(shù)： | 9/81頁 |
| 文件大?。?/td> | 905K |
| 代理商： | MC68HC05LJ5P |
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November 10, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05LJ5
GENERAL DESCRIPTION
MOTOROLA
REV 1
1-7
devices on PA6 and PA7 once enabled are always enabled regardless of pin direc-
tion conguration, unlike pull-down devices on PA0 to PA5 which are activated
only when these pins are congured as input pins.
PA6 and PA7 pins, when congured as output pins, also have slow output falling-
edge transition feature to reduce EMI. The falling-edge transition time is tentatively
set at 250ns typical at a specied load of 500pF, assuming the bus rate is 2MHz.
The slow transition output feature of PA6 and PA7, along with that of PB1 and
PB2, can be enabled or disabled by software. Both PA6 and PA7 pins have
Schmitt trigger input for better noise immunity. VIH and VIL are specied at 2.4V
and 0.8V, respectively.
The slow transition feature of PA6 and PA7 pins can be enabled or disabled by
software. Once enabled, slow transition feature is applied to both pins while in out-
put mode.
1.5.6 PB0-PB5
NOTE
I/O lines PB2 to PB5 are not available on the 16-pin package.
These six I/O lines comprise Port B. PB0, PB3 to PB5 are push-pull I/O lines with
pull-down resistor. PB1 and PB2 are open-drain I/O lines with pull-up resistor.
The state of any line is software programmable and is congured as an input dur-
ing power-on or reset. I/O lines PB1 and PB2 have software programmable pull-up
device whereas PB0, PB3 to PB5 have software programmable pull-down device,
by a mask option. Pull-up devices on PB1 and PB2 lines once enabled are always
enabled regardless of pin direction conguration; unlike pull-down devices on
PB0, PB3-PB5 lines, which are activated only when the pin is congured as input
pin.
Similar to PA6 and PA7, PB1 also has a slow output falling transition feature when
congured as an output line. PB1 has 25mA sink capability at 0.5V VOL.
PB2 output is one clock cycle (250ns if bus rate is 2MHz) late than other I/O pins if
slow output transition feature is enabled. PB2 has 25mA sink capability at 0.5V
VOL.
NOTE
For the 16-pin package, PB1 and PB2 are bonded to the same pin and is labelled
PB1. This PB1 has 50mA sink capability is slow transition feature is enabled and if
they are written with the same value at the same write cycle. The falling transition
time of PB1 is set at 250ns typical at a specied load of 50pF, assuming that the
bus rate is 2MHz. The slow transition feature on this PB1 pin is longer than PB1
pin for the 20-pin package.
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