參數(shù)資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 119/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
Chapter 4. QMC Exceptions
Chapter 4
QMC Exceptions
40
QMC interrupt handling involves two principle data structures—the SCC event register
(SCCE) and the circular interrupt table. Figure 4-1 illustrates the circular interrupt table.
Figure 4-1. Circular Interrupt Table in External Memory
INTBASE (interrupt base) points to the starting location of the queue in external memory,
and INTPTR (interrupt pointer) marks the current empty position available to the RISC
processor. Both pointers are host-initialized global QMC parameters; see Table 2-1. The
entry whose W (wrap) bit is set to 1 marks the end of the queue. When one of the QMC
channels generates an interrupt request, the RISC processor writes a new entry to the queue.
In addition to the channel’s number, this entry contains a description of the exception. The
V (valid) bit is then set and INTPTR is incremented. When INTPTR reaches the entry with
W = 1, INTPTR is reset to INTBASE.
An interrupt is written to the interrupt table only if it survives a mask with the INTMASK
(interrupt mask) register. Following a write to the queue, the QMC protocol updates the
SCC event register (SCCE) according to the type of exception.
V = 1
Interrupt Flags
V = 0
X
V = 0
X
V = 0
X
V = 1
Interrupt Flags
V = 1
Interrupt Flags
V = 1
Interrupt Flags
V = 0
X
V = 0
X
V = 0
X
INTBASE
SOFTWARE POINTER
INTPTR
W = 0
W = 1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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