參數(shù)資料
型號(hào)： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 16/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
8.2 CPM Loading
This section primarily deals with the CPM loading of the MH360 and 860MH. As the CPM
architecture is identical on both devices, the performance for a given clock frequency is
identical. Compared to standard protocols, the QMC protocol places more demands on the
CPM RISC because it requires the CPM to handle all of the bit manipulation normally
implemented with hardware support built into the SCCs.
The SCC operates transparently in QMC mode. The SCC’s main function is serial-to-
parallel conversion of the data stream out of the time slot assigner, and parallel-to-serial
conversion of the data stream gated into the time slot assigner. All bit manipulating is done
in the CPM RISC software or hardware. Thus, the CPM has a much higher load when
operating in QMC mode, even if all time slots are concatenated to one logical channel. This
loading is reected in the measured performance.
Table 8-2 gives loading guidelines. The table assumes a single SCC running at 100% of the
CPM bandwidth. For each protocol supported, the table gives the ratio of the SCC bit rate
versus clock frequency, and the maximum serial throughput at standard frequencies.
SCC1: 10-Mbps Ethernet; SCC2: 16 x 64-Kbps QMC;
SCC3: 16 x 64-Kbps QMC; SCC4: 64-Kbps HDLC.
TDM bit rate = 2.048 Mbps
No
Yes
SCC1: 10-Mbps Ethernet; SCC2: 12 x 64-Kbps QMC;
SCC3: 12 x 64-Kbps QMC; SCC4: 64-Kbps HDLC.
TDM bit rate = 1.544 Mbps
No
Yes
SCC1: 24-channel QMC; SCC2: 24-channel QMC.
Serial bit rate 2 x 1.544 Mbps — 2 x T1
No
Yes
SCC1: 10-Mbps Ethernet SCC2: 24-channel QMC;
SCC3: 24 Channel QMC.
Serial bit rate 2 x 1.544 Mbps — 2 x T1
No
Yes
SCC1: 32-channel QMC; SCC2: 32-channel QMC.
Serial bit rate 2 x 2.048 Mbps (E1/CEPT)
No
Yes
Table 8-2. CPM Performance Table
Protocol
SCC Rate: Clock Frequency
Mbps: MHz
Maximum Serial Throughput
25 MHz
Mbps
33 MHz
Mbps
40 MHz
Mbps
50 MHz
Mbps
Transparent
1 : 3.125 FD
8
10.56
12.8
16
HDLC
1 : 3.125 FD
8
10.56
12.8
16
UART
1 : 10.4 FD
2.4
3.168
3.84
4.8
Table 8-1. Common QMC Configurations (Continued)
Protocols Selected
Frequency Supported
25 MHz
33 MHz
40 MHz
50 MHz
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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