參數資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數： 61/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標準包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應商設備封裝： 357-PBGA（25x25）
包裝： 托盤
Index
INDEX
A
Acronyms and abbreviations, xiii
Alignment
non-octet alignment data, 5-4
B
Bibliography of additional reading, xii
Bit numbering, MC68360, A-1
Buffer descriptor
buffer descriptor tables, 2-4
data buffer pointer, 2-5
placement, 5-7
RxBD, 5-1
TxBD, 5-5
Bus latency and peak load, 8-5
C
Channel
channel addressing capability, 1-2
channel pointers
MCBASE, 2-4
RBASE, 2-4
TBASE, 2-4
time slot assignment, 2-4
TSATRx, 2-9
TSATTx, 2-9
channel-specific parameters, 2-14, 6-18
channel-specific transparent parameters, 2-20
common combinations, 8-1
interrupt processing flow, 4-7
interrupt table entry, 4-5
Circular interrupt table, external memory, 4-1
Commands
receive, 3-2
transmit, 3-1
Configuration difficulties, MC68MH360, 5-20
Conventions, xii
CPM loading, 8-2
D
Data clock generation, C-4
Disabling receiver/transmitter, 6-17
E
E1/T1 frame description, 1-11
Echo mode, 1-5
Errors
global error events, 4-2
SI RAM, 1-10
Ethernet
MC68MH360 configuration, 5-20
routing examples, 1-6–1-9
Exceptions
channel interrupt processing flow, 4-7
interrupt table entry, 4-5
overview, 4-1
TxB, 5-6
F
Features
deleted, 7-1
summary, list, 1-3
Frame sync generation, C-4
Frequently asked questions (FAQ), B-1
G
Global error events
description, 4-2
restart, 4-3, 6-17
Global multichannel parameters, 2-5, 6-18
Global overrun, 4-3
Global underrun, 4-3
I
Interrupt table entry, 4-5, A-3, A-4
Inverted signals, 1-5
ISDN connection to QUICC32, C-1
L
Latency
bus latency and peak load, 8-5
simulated latencies, 8-6
Loading
CPM loading, 8-2
peak load and bus latency, 8-5
Loopback mode, 1-5
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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