參數(shù)資料
型號: MC68MH360ZQ33L
廠商: Freescale Semiconductor
文件頁數(shù): 59/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 44
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
Appendix C. Connecting ISDN Multiple S/T or U Interfaces to QUICC32
C.3.3.2 U-Interface Conguration
Do the following for U-interface conguration:
IDL2 with time slot assigner (TSA enabled in reg. OR6[5–7]; TSA selection in
reg. OR0 to OR5)
Slave mode (DCL & FSC are input) - (pin M/S to GND)
FREQREF enabled at 2.048 MHz (reg. OR8[4] = 1)
C.3.3.3 QUICC32 Conguration
Do the following for QUICC32 conguration:
SCC3 using the QMC protocol for handling the different channels of the
multiplexed IDL2 bus. (D channels are HDLC encoded/decoded and B-channels
can be congured for transparent or HDLC framing)
SCC1 can be congured for Ethernet, HDLC, transparent, or UART.
SCC2 and SCC4 can be congured for HDLC, transparent, or UART.
The SPI is connected to the SCP port of each S/T or U interface for handling
conguration and control information.
For the U interface, the SPI/SCP connection can be replaced by a connection of
the 8-bit parallel port of the U transceiver to the processor bus of the QUICC.
One I/O signal can be dedicated for handling the SCPEN signal of each S/T or
U interface.
One interrupt signal can be dedicated for handling the IRQ signal of each S/T or
U interface.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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