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參數資料
| 型號： | MC68MH360ZQ33L |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 120/158頁 |
| 文件大小： | 0K |
| 描述： | IC MPU QUICC 33MHZ 357-PBGA |
| 標準包裝： | 44 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 357-BBGA |
| 供應商設備封裝： | 357-PBGA（25x25） |
| 包裝： | 托盤 |
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QMC Supplement
Following a request that is not masked out by the INTMASK or the SCCM (SCC mask)
register, an interrupt is generated to the host. The host reads the SCCE to determine the
cause of interrupt. A dedicated SCCE bit (GINT) indicates that at least one new entry was
added to the queue. After clearing GINT, the host starts processing the queue. The host then
clears this entry’s valid bit (V). The host follows this procedure until it reaches an entry with
V = 0, indicating an invalid entry.
NOTE
It is important that the user clear all interrupt ags in a queue
entry even though its valid bit may be cleared since old ags are
not necessarily overwritten with each new event.
4.1 Global Error Events
A global error affects the operation of the SCC. A global error can occur for two reasons—
serial data rates being too high for the CPM to handle, and CPM bus latency being too long
for correct FIFO operation.
There are two global errors— global transmitting underrun (GUN) and global receiver
overrun (GOV). GUN indicates that transmission has failed due to lack of data; and GOV
indicates that the receiver has failed because the RISC processor did not write previous data
to the receive buffer. In both cases, it is unknown which channel(s) are affected.
Nonglobal, individual channel errors are handled differently. See Section 4.3, “Interrupt
Table Entry,” for underrun and overrun in a specic channel.
The incoming data to the CPM is governed by transfers between the SCC and the SI. Every
transfer in either direction causes a request to the CPM state machine. If requests are
received too quickly, the CPM crashes due to an overload of serial data. This causes a global
error depending on whether it happened in the transmit side or the receive side. This error
affects all QMC channels.
The other error condition is bus latency. A receiving channel submits data to the FIFO for
transfer to external memory as long as the channel operates normally. If the bus latency for
the SDMA channels is too long and the receive FIFO is lled and overwritten, a receiver
overow occurs. The overwriting channels cannot be traced, affecting entire QMC
operation.
A similar situation can occur during transmission when the SDMA cannot ll the FIFO
from external memory because of bus latency. Again, it cannot be determined which
channel is underrun, and the whole QMC operation is affected.
Global errors are unlikely to occur in normal system operation, if correct serial speed is
used. The only area of concern is data movement between the FIFO and external memory.
To avoid problems, the user must understand the bus arbitration mechanism of the QUICC
and meet the latency requirements; see Chapter 8, “Performance,” for more information.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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