參數(shù)資料
型號(hào): MC68MH360ZQ33L
廠商: Freescale Semiconductor
文件頁數(shù): 23/158頁
文件大?。?/td> 0K
描述: IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝: 44
系列: M683xx
處理器類型: M683xx 32-位
速度: 33MHz
電壓: 5V
安裝類型: 表面貼裝
封裝/外殼: 357-BBGA
供應(yīng)商設(shè)備封裝: 357-PBGA(25x25)
包裝: 托盤
Chapter 9. Multi-Subchannel (MSC) Microcode
NOTE
As the L bit (bit 11 of a time slot assignment table entry) is
taken from the original channel pointer eld, the addressing
capability of the QMC is reduced from 6 bits (64 channels) to
5 bits (32 channels) for receive and transmit.
Figure 9-2. Two-Bit Subchannel Implementation with MSC Microcode
9.3 Programming the MSC Protocol
The MSC protocol conguration is identical to the QMC conguration with the exception
of the time slot assignment tables. Figure 9-3 shows the addition of the L bit needed for the
MSC conguration. Note that it is possible to have up to 32 channels coming from any
permutation of the time slots.
TS0
TS1
TS2
TS31
8 BITS
SCC1
LC2A
LC2B
LC2C
LC2D
Masking performed by a single SCC to create four 2-bit channels
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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