參數(shù)資料
型號： MC68MH360ZQ33L
廠商： Freescale Semiconductor
文件頁數(shù)： 69/158頁
文件大?。?/td> 0K
描述： IC MPU QUICC 33MHZ 357-PBGA
標(biāo)準(zhǔn)包裝： 44
系列： M683xx
處理器類型： M683xx 32-位
速度： 33MHz
電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 357-BBGA
供應(yīng)商設(shè)備封裝： 357-PBGA（25x25）
包裝： 托盤
QMC Supplement
works transparently, not participating in any QMC protocol functions. The SCC only
performs the parallel-to-serial conversion and adds elasticity through its FIFO memory. The
CPM, with its special enhanced microcode and additional dedicated hardware for framing
and masking support, does all of the protocol processing for each of the 64 channels. Note
that it is executed without intervention from the on-board CPU. Figure 1-1 illustrates the
QMC’s multichannel capability. Note that each SCC can support up to 64 channels from
the TDM; however, there are limitations depending on the device used. This is summarized
in Section 1.3, “QMC Features.”
Each SCC can work in QMC mode, either alone or together in any combination. The larger
FIFO of SCC1 yields the best performance and is therefore recommended for QMC
operation. One TDM connection can be routed to one or more SCCs operating in QMC
mode, with each SCC operating on different time slots. It is possible to use both TDMs for
QMC with combined routing to one SCC or to separate SCCs. When using two TDMs
connected to one SCC, restrictions such as using common clocks and sync inputs apply; it
is also important to avoid collisions by separating the serial interface (SI) routing.
Figure 1-1. QMC Channel Addressing Capability
CPM
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
Serial Interface
64
1
64
1
64
1
64
1
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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