參數(shù)資料
型號(hào)： MC94MX21DVKN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 350 MHz, MICROPROCESSOR, PBGA289
封裝： 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁(yè)數(shù)： 16/98頁(yè)
文件大?。?/td> 1326K
代理商： MC94MX21DVKN3R2
Specifications
MC94MX21 Technical Data, Rev. 1.
5
Freescale Semiconductor
23
Figure 8. BMI Drives Clock, MMD Read BMI Timing
(MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1)
Note: In this mode, the max frequency of the BMI_CLK/CS can be up to 36MHz (double as max data pad speed).
Note: The BMI_CLK/CS can only be divided by 2,4,8,16 from HCLK.
3.8.1.4
MMD Write BMI Timing
Figure 9 shows the MMD write BMI timing when BMI drives BMI_CLK/CS.
When the BMI_WRITE signal is asserted, the BMI can write a 1 to READ bit of control register to issue
a WRITE cycle. This bit is cleared automatically when the WRITE operation is completed. In a WRITE
burst the MMD will write COUNT+1 data to the BMI. The user can issue another WRITE operation if the
MMD still has data to write after the first operation completed.
The BMI can latch the data either at falling edge or the next rising edge of the BMI_CLK/CS according to
the DATA_LATCH bit. When the DATA_LATCH bit is set, the BMI latch data at the next rising edge and
latch the last data using the internal clock.
BMI_WRITE signal can not be negated when the WRITE operation is proceeding.
Table 15. MMD Read BMI Timing Table when BMI Drives Clock
Item
Symbol
Minimum
Typical
Maximum
Unit
Transfer data setup time
Tds
2
–
8
ns
Transfer data hold time
Tdh
2
–
8
ns
Read_req hold time
Trh
2
–
18
ns
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
TxD1
TxD2
Last TxD
1T
Tds
Trh
DMA or CPU write data to TxFIFO
Tdh
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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