參數(shù)資料
型號: MC94MX21DVKN3R2
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 350 MHz, MICROPROCESSOR, PBGA289
封裝: 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁數(shù): 9/98頁
文件大?。?/td> 1326K
代理商: MC94MX21DVKN3R2
Specifications
MC94MX21 Technical Data, Rev. 1.
5
Freescale Semiconductor
17
3.5
DPLL Timing Specifications
Parameters of the DPLL are given in Table 10. In this table, Tref is a reference clock period after the
predivider and Tdck is the output double clock period.
Table 10. DPLL Specifications
Parameter
Test Conditions
Minimum
Typical
Maximum
Unit
Reference clock frequency range
Vcc = 1.7V
16
320
MHz
Pre-divider output clock frequency
range
Vcc = 1.7V
16
32
MHz
Double clock frequency range
Vcc = 1.7V
220
560
MHz
Pre-divider factor (PD)
1
16
Total multiplication factor (MF)
Includes both integer and fractional parts
5
15
MF integer part
5
15
MF numerator
Should be less than the denominator
0
1022
MF denominator
1
1023
Frequency lock-in time after
full reset
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
350
400
450
Tref
Frequency lock-in time after
partial reset
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
220
280
330
Tref
Phase lock-in time after
full reset
FPL mode and integer MF
(does not include pre-multi lock-in time)
480
530
580
Tref
Phase lock-in time after
partial reset
FPL mode and integer MF
(does not include pre-multi lock-in time)
360
410
460
Tref
Frequency jitter (p-p)
0.02
0.03
2Tdck
Phase jitter (p-p)
Integer MF, FPL mode, Vcc=1.7V
1.0
1.5
ns
Power dissipation
FOL mode, integer MF,
fdck = 560 MHz, Vcc = 1.7V
–1.5
mW
(Avg)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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