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參數(shù)資料
| 型號： | MC94MX21DVKN3R2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 350 MHz, MICROPROCESSOR, PBGA289 |
| 封裝： | 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289 |
| 文件頁數(shù)： | 17/98頁 |
| 文件大小： | 1326K |
| 代理商： | MC94MX21DVKN3R2 |
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MC94MX21 Technical Data, Rev. 1.
5
24
Freescale Semiconductor
Specifications
Figure 9. BMI Drives Clock, MMD Write BMI Timing
(MASTER_MODE_SEL=0, MMD_MODE_SEL=1, MMD_CLKOUT=1)
Note: The BMI_CLK/CS can only be up to 30MHz if BMI latch data at the falling edge and can be up to 36MHz (double as max
data pad speed) if BMI latch data at the next rising edge.
Note: Tds1 is the receive data setup time when BMI latch data at the falling edge.
Note: Tds2 is the receive data setup time when BMI latch data at the next rising edge.
3.8.2
Connecting BMI to External Bus Master Devices
In this mode both MASTER_SEL bit and MMD_MODE_SEL bit are cleared and the MMD_CLKOUT
bit is no useful. BMI_WRITE and BMI_CLK/CS are input signals driving by the external bus master. The
Output signal BMI_READ_REQ can be used as an interrupt signal to inform external bus master that data
is ready in the BMI TxFIFO for a read access. The external bus master can write data to the BMI RxFIFO
anytime since the CPU or DMA can move data out from RxFIFO much faster than the BMI interface. An
overflow interrupt is generated if RxFIFO overflow is detected. Once this happens, the new coming data
is ignored.
Each falling edge of BMI_CLK/CS will determine if the current cycle is read or write cycle. It drives data
and enables data out if BMI_WRITE is logic high. The D_EN signal remains active only while BMI_CLK/
CS is logic low and BMI_WRITE is logic high.
Each rising edge of BMI_CLK/CS will determine if data should be latched to RxFIFO from the data bus.
Table 16. MMD Write BMI Timing Table when BMI Drives Clock
Item
Symbol
Minimum
Typical
Maximum
Unit
Receive data setup time1
Tds1
14
–
ns
Receive data setup time2
Tds2
14
–
ns
Can be asserted any time
BMI_CLK/CS
BMI_READ_REQ
BMI_WRITE
BMI_D[15:0]
RxD1
RxD2
Last RxD
Tds1
Tds2
A 1 is written to READ bit of control register
Total has COUNT+1 clocks in one burst
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MC94MX21DVKN3R2 | 制造商:Freescale Semiconductor 功能描述:32-bit Embedded Microprocessors |
| MC950 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:INTEGRATED CIRCUITS |
| MC951 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:INTEGRATED CIRCUITS |
| MC952 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:INTEGRATED CIRCUITS |
| MC953 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:INTEGRATED CIRCUITS |
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