參數(shù)資料
型號(hào)： MC94MX21DVKN3R2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 350 MHz, MICROPROCESSOR, PBGA289
封裝： 14 X 14 MM, 1.41 MM HEIGHT, 0.65 MM PITCH, LEAD FREE, PLASTIC, BGA-289
文件頁數(shù)： 94/98頁
文件大小： 1326K
代理商： MC94MX21DVKN3R2
MC94MX21 Technical Data, Rev. 1.
94
Freescale Semiconductor
Specifications
Figure 84. Sensor Output Data on Pixel Clock Rising Edge
CSI Latches Data on Pixel Clock Falling Edge
3.22.3
Calculation of Pixel Clock Rise/Fall Time
The limitation on pixel clock rise time/fall time is not specified. It should be calculated from the hold time
and setup time based on the following assumptions:
Rising-edge latch data
max rise time allowed = (positive duty cycle - hold time)
max fall time allowed = (negative duty cycle - setup time)
In most of case, duty cycle is 50 / 50, therefore:
max rise time = (period / 2 - hold time)
max fall time = (period / 2 - setup time)
For example: Given pixel clock period = 10ns, duty cycle = 50 / 50, hold time = 1ns, setup time = 1ns.
positive duty cycle = 10 / 2 = 5ns
≥ max rise time allowed = 5 - 1 = 4ns
negative duty cycle = 10 / 2 = 5ns
≥ max fall time allowed = 5 - 1 = 4ns
Falling-edge latch data
max fall time allowed = (negative duty cycle - hold time)
max rise time allowed = (positive duty cycle - setup time)
Table 45. Non-Gated Clock Mode Parameters1
1. HCLK = AHB System Clock, THCLK = Period of HCLK
Number
Parameter
Minimum
Maximum
Unit
1
csi_vsync to csi_pixclk
9 * THCLK
–ns
2
csi_d setup time
1
–
ns
3
csi_d hold time
1
–
ns
4
csi_pixclk high time
THCLK
–ns
5
csi_pixclk low time
THCLK
–ns
6
csi_pixclk frequency
0
HCLK / 2
MHz
1
VSYNC
PIXCLK
DATA[7:0]
2
3
6
5
4
Valid Data
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MC94MX21DVKN3
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