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ML674001 Series/ML675001 Series User’s Manual
Chapter 18
UART with FIFO(16byte)
18-26
18.3.3
Generating Baud Rate Clock
The following is the formula for calculating the baud rate frequency.
Baud rate frequency = CCLK/(DL[15:0] × 16)
Maximum baud rate clock depends on the software, the application, the system load and etc.
But there is
the capability of the transmit/receive baud rate with DL=”2” setting in an ideal condition (ex. UART test)
as long as in a small value of the baud rate deviation.
Note:
A divisor (DL[15:0]) of 1 is not allowed. The setting must be either 0, to stop the clock, or a value of 2
or more.
The frequency of CCLK should be set up less than or equal to the frequency of HCLK.
The following Table lists DL settings for CPU clock and baud rate combinations.
CCLK=60MHz *
CCLK = 33MHz
CCLK = 20MHz
CCLK = 8MHz
Baud
Rate
DL [H]
Deviatio
n (%)
DL [H]
Deviatio
n (%)
DL [H]
Deviatio
n (%)
DL [H]
Deviatio
n (%)
50
A122
0.00000
61A8
0.00000
2710
0.00000
75
C350
0.00000
6B6C
0.00000
411B
–0.00200
1A0B
–0.00500
110
852B
–0.00027
493E
0.00000
2C64
–0.00320
11C1
0.01000
134.5
6CE9
0.00015
3BE7
–0.00279
244E
–0.00344
0E85
0.01270
150
61A8
0.00000
35B6
0.00000
208D
0.00400
0D05
0.01000
300
30D4
0.00000
1ADB
0.00000
1047
–0.00800
0683
–0.02000
600
186A
0.00000
0D6E
–0.01454
0823
0.01600
0341
0.04002
1200
0C35
0.00000
06B7
–0.01454
0412
–0.03199
01A1
–0.07994
1800
0823
0.01600
047A
–0.01454
02B6
0.06404
0116
–0.07994
2000
0753
0.00000
0407
0.02425
0271
0.00000
00FA
0.00000
2400
061A
0.03200
035B
–0.04366
0209
–0.03199
00D0
0.16026
3600
0412
–0.03200
023D
–0.01454
015B
0.06404
008B
–0.07994
4800
030D
0.03200
01AE
–0.07267
0104
0.16026
0068
0.16026
7200
0209
–0.03200
011E
0.16026
00AE
–0.22340
0045
0.64412
9600
0187
–0.09600
00D7
–0.07267
0082
0.16026
0034
0.16026
19200
00C3
0.16000
006B
0.39428
0041
0.16026
001A
0.16026
38400
0062
–0.35200
0036
–0.53530
0021
–1.35732
000D
0.16026
56000
0043
–0.05333
0025
–0.45849
0016
1.46104
0009
–0.79365
115200
0021
–1.37600
0012
–0.53530
000B
–1.35732
—
Note:
*As for the notation of
'CCLK=60MHz', only in the case of ML675001 series.