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ML674001 Series/ML675001 Series User’s Manual
Chapter 1 Introduction
1-1
Chapter 1
Introduction
1.
1.1 Features
This high-performance CMOS 32-bit micro-controller combines the 32-bit ARM7TDMI
TM
core, a RISC CPU
developed by Advanced RISC Machines Limited (ARM), with a DMA controller, serial ports, PWM generator,
analog-to-digital converter, 16-bit timers, and other peripheral functions on a single LSI.
In addition to 32-bit data processing, this LSI includes internal RAM and onboard peripherals that make it ideal for
such embedded control applications as PC peripherals and communication terminals.
Finally, there is a built-in external memory controller for directly connecting ROM, SRAM, SDRAM, other
memory types, and peripheral devices.
The following is a list of features.
CPU
—
32-bit RISC CPU (ARM7TDMI)
—
Built-in 8KB unified cache (ML675001 series only)
—
Little endian byte order
—
Operating frequency:
ML674001 series :1 MHz to 33 MHz
ML675001 series :1 MHz to 60 MHz
—
Instruction set: Free switching between a highly dense 32-bit instruction set and a 16-bit subset offering
higher object code efficiency
—
General-purpose registers: 32-bit
× 31
—
Barrel shifter: Simultaneous ALU and barrel shift operations in the same instruction
—
Multiplier (32-bit
× 8-bit)
—
JTAG interface for debugging
Built-in Memory
—
SRAM 32Kbytes (8K x 32bits), 1 cycle access
—
FLASH memory
ML674001: ROM-less version
ML67Q4002: 256Kbytes (128K x 16bits)
ML67Q4003: 512Kbytes (256K x 16bits)
ML675001: ROM-less version
ML67Q5002: 256Kbytes (128K x 16bits)
ML67Q5003: 512Kbytes (256K x 16bits)
Interrupt Controller
—
One fast interrupt (FIQ) source (external)
—
27 interrupt (IRQ) sources (23 internal and 4 external)
—
Independent masking for each FIQ and IRQ source
—
Independent interrupt priority level settings for each IRQ source
—
Priority control blocking IRQ requests with priority levels at or below those for interrupt requests
currently being processed
—
Choice of level or edge sensing for external IRQ sources EXINT0 to EXINT3.
Timers
—
One 16-bit system timer
—
Six 16-bit auto reload timers
Independent clock settings for each timer
Independent choice of one shot or interval timer operation for each timer
—
Maximum period: 30 ms or more
Watchdog Timer
—
One 16-bit timer
—
Choice of interval or watchdog timer operation
—
Choice of interrupt or reset upon overflow
—
Maximum period: 200 ms or more