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ML674001 Series/ML675001 Series User’s Manual
Table of Contents
iii
Chapter 8
Interrupt Controller
8.1 Overview ........................................................................................................................................................ 8-1
8.1.1
Components ............................................................................................................................................ 8-2
8.1.2
Pin List.................................................................................................................................................... 8-3
8.1.3
Register List............................................................................................................................................ 8-3
8.2 Interrupt Sources............................................................................................................................................. 8-4
8.2.1
External Fast Interrupt (EFIQ_N) ........................................................................................................... 8-4
8.2.2
External Interrupts (EXINT[n]) .............................................................................................................. 8-4
8.2.3
Internal Interrupts (IRQn) ....................................................................................................................... 8-4
8.2.4
Interrupt Source List ............................................................................................................................... 8-5
8.3 Interrupt Levels............................................................................................................................................... 8-6
8.4 Register Descriptions...................................................................................................................................... 8-7
8.4.1
IRQ Register (IRQ)................................................................................................................................. 8-7
8.4.2
Software Interrupt Register (IRQS) ........................................................................................................ 8-8
8.4.3
FIQ Register (FIQ).................................................................................................................................. 8-9
8.4.4
FIQRAW Register (FIQRAW) ............................................................................................................. 8-10
8.4.5
FIQ Enable Register (FIQEN) .............................................................................................................. 8-11
8.4.6
IRQ Number Register (IRN)................................................................................................................. 8-12
8.4.7
Current Interrupt Level Register (CIL) ................................................................................................. 8-13
8.4.8
Interrupt Level Control Register 0 (ILC0) ............................................................................................ 8-14
8.4.9
Interrupt Level Control Register 1 (ILC1) ............................................................................................ 8-16
8.4.10
Current Interrupt Level Clear Register (CILCL) .................................................................................. 8-18
8.4.11
Current Interrupt Level Encode Register (CILE).................................................................................. 8-19
8.4.12
IRQ Clear Register (IRCL) ................................................................................................................... 8-20
8.4.13
IRQA Register (IRQA) ......................................................................................................................... 8-21
8.4.14
IRQ Detection Mode Setting Register (IDM) ....................................................................................... 8-23
8.4.15
Interrupt Level Control Register (ILC) ................................................................................................. 8-24
8.4.16
Register Settings for Interrupt Sources ................................................................................................. 8-26
8.5 Description of Operation .............................................................................................................................. 8-27
8.5.1
External Fast Interrupt (EFIQ_N) ......................................................................................................... 8-27
8.5.2
External and Internal Interrupts (IRQn)................................................................................................ 8-28
8.5.3
Nested Interrupts and Re-Entrant Interrupt Service Routines............................................................... 8-30
8.5.4
Important Notes on Interrupts ............................................................................................................... 8-31
8.5.5
Waking from HALT and STANDBY Modes ....................................................................................... 8-32
8.5.6
Error Response...................................................................................................................................... 8-33
8.5.7
Interrupt Response Times ..................................................................................................................... 8-33
8.6 Interrupt Acceptance Timing Charts............................................................................................................. 8-34
8.6.1
FIQ Interrupt Timing Chart .................................................................................................................. 8-34
8.6.2
IRQ Interrupt Timing Chart (nIR0 to nIR15) ....................................................................................... 8-34
8.6.3
IRQ Interrupt Timing Chart (nIR16 to nIR31) ..................................................................................... 8-36
Chapter 9
Cache Memory
9.1 Overview ........................................................................................................................................................ 9-1
9.1.1
Configuration .......................................................................................................................................... 9-1
9.1.2
List of Control Registers......................................................................................................................... 9-2
9.2 Description of Control Registers .................................................................................................................... 9-2
9.2.1
Cache Lock Control Register (CON)...................................................................................................... 9-2
9.2.2
Cacheable Register (CACHE) ................................................................................................................ 9-4
9.2.3
FLUSH Register (FLUSH) ..................................................................................................................... 9-5
9.3 Description of Operations............................................................................................................................... 9-6
9.3.1
Initialization of Cache Memory .............................................................................................................. 9-6
9.3.2
Cacheable/Non-cacheable Setting........................................................................................................... 9-6
9.3.3
Description of operations........................................................................................................................ 9-6