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ML674001 Series/ML675001 Series User’s Manual
Chapter 3
Address Mapping
3-2
3.2
Address Map
3.2.1 ML674001 series address map
Bank
Address
FFFF FFFF
F800_0000
F800 0000
F600_0000
External I/O 3
F400 0000
External I/O 2/3
F400_0000
External I/O 2
F000 0000
External I/O 0/1
F200_0000
External I/O 1
F000_0000
External I/O 0
E800 0000
E000 0000
D000_0000
D800 0000
CC00_0000
D000 0000
C800_0000
C800 0000
C000 0000
B800 2020
B800 0000
B800 2000
SIO control register
B800 1020
(reserved)
B000 0000
B800 1000
System timer control register
B800 0020
(reserved)
A800 0000
B800 0000
System control register
A000 0000
B800 0000
B7F0 0000
Auto reload timer control register
9800 0000
B7E0 0000
WDT control register
B7D0 0000
PWM control register
9000 0000
B7B0 1000
Synchronous SIO control register
B7B0 0000
UART control register
8800 0000
B7A0 1000
Port control register
B780 1000
(reserved)
8000 0000
B780 0000
I2C control register
7C00_0000
(reserved)
B710_0000
7830_0000
AHB standard IO
7800_0000
uPlat Core I/O
B700_0000
Chip configuration control register
7000 0000
B600 2000
B600 1000
Analog-to-digital converter control register
6800 0000
B000_0000
6000 0000
5800 0000
8000 0000
5000 0000
7C00 0000
4800 0000
7BF0 0000
Expansion interrupt control register
7BE0 0000
DMA controller control register
4000 0000
7830 0000
3800 0000
7820 0000
(reserved)
7818 0000
DRAM controller control register
3000 0000
7810 0000
External memory and I/O access control register
Internal RAM
7800 0030
(reserved)
2800 0000
(mirror of bank 2)
7800 0000
Interrupt control register
External SRAM
2000 0000
(mirror of bank 26)
5000_0000
1800 0000
(reserved)
Internal RAM
4800_1000
1000 0000
4800_0000
BootROM(4KB)
0800 0000
Remappable ROM/RAM
0000 0000
(AHB / Ext.)
(reserved)
27
26
25
21
22
23
24
17
18
31
30
28
29
12
19
20
13
14
15
16
9
8
10
11
4
5
6
7
0
1
2
3
(reserved)
External ROM/MCP Flash ROM (refer to table
3-1)
External DRAM
MCP Flash ROM/External ROM (refer to table
3-1)
(reserved)
Core APB I/O
(reserved)
External SRAM
External ROM
Standard APB I/O
(reserved)
External
A
PB
A
HB
Processor
Note:
Banks 4 and 5 respectively mirror banks 26 (external SRAM) and (internal RAM) so that software can treat the
two as a single, contiguous memory region.
Do not carry out access to the reserved regions in the address
map.
Operation is not guaranteed when accessing.