參數(shù)資料
型號: MPC7457
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 15/68頁
文件大?。?/td> 1755K
代理商: MPC7457
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
15
Electrical and Thermal Characteristics
5.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the MPC7457. After fabrication, functional parts are
sorted by maximum processor core frequency as shown in Section 1.5.2.1, “Clock AC Specifications,” and tested
for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus
(SYSCLK) frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core
frequency; see Section 1.11, “Ordering Information.”
5.2.1
Clock AC Specifications
Table 8
provides the clock AC timing specifications as defined in
Figure 6
and represents the tested operating
frequencies of the devices. The maximum system bus frequency, f
SYSCLK
, given in
Table 8
is considered a practical
maximum in a typical single-processor system. The actual maximum SYSCLK frequency for any application of the
MPC7457 will be a function of the AC timings of the MPC7457, the AC timings for the system controller, bus
loading, printed-circuit board topology, trace lengths, and so forth, and may be less than the value given in
Table 8
.
For information regarding the use of spread spectrum clock generators, see
Section 9.1.3, “System Bus Clock
(SYSCLK) and Spread Spectrum Sources
.” PLL configuration and bus-to-core multiplier information is found in
Section 9.1.1, “Core Clocks and PLL Configuration
.”
Deep Sleep Mode (PLL Disabled)
Typical
5.0
5.0
5.0
5.0
W
1, 2
Notes:
1. These values apply for all valid processor bus and L3 bus ratios. The values do not include I/O supply power (OV
DD
and
GV
DD
) or PLL supply power (AV
DD
). OV
DD
and GV
DD
power is system dependent, but is typically <5% of V
DD
power. Worst
case power consumption for AV
DD
< 3 mW.
2. Typical power is an average value measured at the nominal recommended V
DD
(see
Table 4
) and 65
°
C while running the
Dhrystone 2.1 benchmark and achieving 2.3 Dhrystone MIPs/MHz.
3. Maximum power is the average measured at nominal V
DD
and maximum operating junction temperature (see
Table 4
) while
running an entirely cache-resident, contrived sequence of instructions which keep all the execution units maximally busy.
4. Doze mode is not a user-definable state; it is an intermediate state between full-power and either nap or sleep mode. As a
result, power consumption for this mode is not tested.
Table 8. Clock AC Timing Specifications
At recommended operating conditions. See
Table 4
.
Characteristic
Symbol
Maximum Processor Core Frequency
Unit
Notes
867 MHz
1000 MHz
1200 MHz
1267 MHz
Min
Max
Min
Max
Min
Max
Min
Max
Processor frequency
f
core
600
867
600
1000
600
1200
600
1267
MHz
1
VCO frequency
f
VCO
1200
1733
1200
2000
1200
2400
1200
2534
MHz
1
SYSCLK frequency
f
SYSCLK
33
167
33
167
33
167
33
167
MHz
1, 2
Table 7. Power Consumption for MPC7457 (continued)
Processor (CPU) Frequency
Unit
Notes
867 MHz
1000 MHz
1200 MHz
1267 MHz
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