參數(shù)資料
型號: MPC7457
廠商: 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述: RISC Microprocessor Hardware Specifications
中文描述: RISC微處理器硬件規(guī)格
文件頁數(shù): 51/68頁
文件大?。?/td> 1755K
代理商: MPC7457
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
Freescale Semiconductor
51
System Design Information
The circuit should be placed as close as possible to the AV
DD
pin to minimize noise coupled from nearby circuits.
It is often possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of the 360 CBGA
footprint and very close to the periphery of the 483 CBGA footprint, without the inductance of vias.
Figure 24. PLL Power Supply Filter Circuit
NOTE
Previous revisions of this document required a 400
resistor for Rev. 1.1 (Rev. B)
devices instead of the 10
resistor shown above. All production devices require a
10
resistor. For more information, see the
MPC7450 Family Chip Errata for the
MPC7457 and MPC7447
.
9.3
Decoupling Recommendations
Due to the MPC7457 dynamic power management feature, large address and data buses, and high operating
frequencies, the MPC7457 can generate transient power surges and high frequency noise in its power supply,
especially while driving large capacitive loads. This noise must be prevented from reaching other components in the
MPC7457 system, and the MPC7457 itself requires a clean, tightly regulated source of power. Therefore, it is
recommended that the system designer place at least one decoupling capacitor at each V
DD
, OV
DD
, and GV
DD
pin
of the MPC7457. It is also recommended that these decoupling capacitors receive their power from separate V
DD
,
OV
DD
/GV
DD
, and GND power planes in the PCB, utilizing short traces to minimize inductance. If compromises
must be made due to board constraints, V
DD
pins should receive the highest priority for decoupling.
These capacitors should have a value of 0.01 or 0.1 μF. Only ceramic surface mount technology (SMT) capacitors
should be used to minimize lead inductance, preferably 0508 or 0603 orientations where connections are made along
the length of the part. Consistent with the recommendations of Dr. Howard Johnson in
High Speed Digital Design:
A Handbook of Black Magic
(Prentice Hall, 1993) and contrary to previous recommendations for decoupling
Freescale microprocessors, multiple small capacitors of equal value are recommended over using multiple values of
capacitance.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the
V
DD
, GV
DD
, and OV
DD
planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors
should have a low equivalent series resistance (ESR) rating to ensure the quick response time necessary. They should
also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk
capacitors: 100–330 μF (AVX TPS tantalum or Sanyo OSCON).
9.4
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level.
Unused active low inputs should be tied to OV
DD
. Unused active high inputs should be connected to GND. All NC
(no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V
DD
, OV
DD
, GV
DD
, and GND pins in the MPC7457.
If the L3 interface is not used, GV
DD
should be connected to the OV
DD
power plane, and L3VSEL should be
connected to BVSEL; the remainder of the L3 interface may be left unterminated.
V
DD
AV
DD
10
2.2 μF
2.2 μF
GND
Low ESL Surface Mount Capacitors
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