- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359188 > MPC7457 (飛思卡爾半導(dǎo)體(中國)有限公司) RISC Microprocessor Hardware Specifications PDF資料下載
參數(shù)資料
| 型號： | MPC7457 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | RISC Microprocessor Hardware Specifications |
| 中文描述： | RISC微處理器硬件規(guī)格 |
| 文件頁數(shù)： | 24/68頁 |
| 文件大?。?/td> | 1755K |
| 代理商： | MPC7457 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
24
Freescale Semiconductor
Electrical and Thermal Characteristics
5.2.4.2
L3 Bus AC Specifications for DDR MSUG2 SRAMs
When using DDR MSUG2 SRAMs at the L3 interface, the parts should be connected as shown in
Figure 9
. Outputs
from the MPC7457 are actually launched on the edges of an internal clock phase-aligned to SYSCLK (adjusted for
core and L3 frequency divisors). L3_CLK0 and L3_CLK1 are this internal clock output with 90° phase delay, so
outputs are shown synchronous to L3_CLK0 and L3_CLK1. Output valid times are typically negative when
referenced to L3_CLK
n
because the data is launched one-quarter period before L3_CLK
n
to provide adequate setup
time at the SRAM after the delay-matched address, control, data, and L3_CLK
n
signals have propagated across the
printed-wiring board.
Inputs to the MPC7457 are source-synchronous with the CQ clock generated by the DDR MSUG2 SRAMs. These
CQ clocks are received on the L3_ECHO_CLK
n
inputs of the MPC7457. An internal circuit delays the incoming
L3_ECHO_CLK
n
signal such that it is positioned within the valid data window at the internal receiving latches. This
delayed clock is used to capture the data into these latches which comprise the receive FIFO. This clock is
asynchronous to all other processor clocks. This latched data is subsequently read out of the FIFO synchronously to
the processor clock. The time between writing and reading the data is set by the using the sample point settings
defined in the L3CR register.
Table 13
provides the L3 bus interface AC timing specifications for the configuration as shown in
Figure 9
,
assuming the timing relationships shown in
Figure 10
and the loading shown in
Figure 8
.
L3DOH
n
L3_DATA[
n
:
n
+7],
L3_DP[
n
/8]
0b000
t
L3CHDV
,
t
L3CLDV
0
t
L3CHDX
,
t
L3CLDX,
0
ps
4
0b001
+ 50
+ 50
0b010
+ 100
+ 100
0b011
+ 150
+ 150
0b100
+ 200
+ 200
0b101
+ 250
+ 250
0b111
+ 300
+ 300
0b111
+ 350
+ 350
Notes:
1. See the
MPC7450 RISC Microprocessor Family User’s Manual
for specific information regarding L3OHCR.
2. See
Table 13
and
Table 14
for more information.
3. Approximate delay verified by simulation; not tested or characterized.
4. Default value.
5. Increasing values of L3CLK
n
_OH delay the L3_CLK
n
signal, effectively decreasing the output valid and output hold times
of all signals latched relative to that clock signal by the SRAM; see
Figure 9
and
Figure 11
.
Table 12. Effect of L3OHCR Settings on L3 Bus AC Timing (continued)
At recommended operating conditions. See
Table 4
.
Field Name
1
Affected Signals
Value
Output Valid Time
Output Hold Time
Unit
Notes
Parameter
Symbol
2
Change
3
Parameter
Symbol
2
Change
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MPC7457EC | RISC Microprocessor Hardware Specifications |
| MPC8241TZQ200C | Intergrated Processor Hardware Specifications |
| MPC8241TZQ266C | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; Number of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| MPC8241TZQ266D | Circular Connector; MIL SPEC:MIL-C-26482, Series I, Solder; Body Material:Aluminum; Series:PT06; No. of Contacts:30; Connector Shell Size:18; Connecting Termination:Solder; Circular Shell Style:Straight Plug; Body Style:Straight |
| MPC8241 | Intergrated Processor Hardware Specifications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MPC7457EC | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:RISC Microprocessor Hardware Specifications |
| MPC745BPX300LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC745BPX350LE | 功能描述:微處理器 - MPU 255 PBGAREV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC745BVT300LE | 功能描述:微處理器 - MPU GF REV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC745BVT350LE | 功能描述:微處理器 - MPU GF REV2.8105C RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。