參數(shù)資料
型號： MPC7457
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： RISC Microprocessor Hardware Specifications
中文描述： RISC微處理器硬件規(guī)格
文件頁數(shù)： 28/68頁
文件大?。?/td> 1755K
代理商： MPC7457
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 5
28
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See
Table 4
.
Parameter
Symbol
All Revisions and L3 I/O
Voltage Modes
Unit
Notes
Min
Max
L3_CLK rise and fall time
t
L3CR
, t
L3CF
—
0.75
ns
1, 2
Setup times: Data and parity
t
L3DVEH
0.1
—
ns
2, 3
Input hold times: Data and parity
t
L3DXEH
—
0.7
ns
2, 3
Valid times: Data and parity
t
L3CHDV
—
2.5
ns
2, 4, 5
Valid times: All other outputs
t
L3CHOV
—
1.8
ns
5
Output hold times: Data and parity
t
L3CHDX
1.4
—
ns
2, 4, 5
Output hold times: All other outputs
t
L3CHOX
1.0
—
ns
2, 5
L3_CLK to high impedance: Data and parity
t
L3CHDZ
—
3.0
ns
2
L3_CLK to high impedance: All other outputs
t
L3CHOZ
—
3.0
ns
2
Notes
:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GV
DD
.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLK
n
(see
Figure 10
). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLK
n
to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
load (see
Figure 10
).
5. Assumes default value of L3OHCR. See
Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications
,” for
more information.
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