參數(shù)資料
型號(hào): MPC8308CZQAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類(lèi): 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, MAPBGA-473
文件頁(yè)數(shù): 3/88頁(yè)
文件大小: 2550K
代理商: MPC8308CZQAGD
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Freescale Semiconductor
11
DDR2 SDRAM
Table 15 provides the current draw characteristics for MVREF.
6.2
DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR2 SDRAM interface.
6.2.1
DDR2 SDRAM Input AC Timing Specifications
Table 16 provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8V.
Table 17 provides the input AC timing specifications for the DDR2 SDRAM interface.
Table 15. Current Draw Characteristics for MVREF
Parameter/Condition
Symbol
Min
Max
Unit
Note
Current draw for MVREF
IMVREF
500
μA1
Note:
1. The voltage regulator for MVREF must be able to supply up to 500 μA current.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8 V Interface
At recommended operating conditions with GVDD of 1.8 ± 100 mV
Parameter
Symbol
Min
Max
Unit
Notes
AC input low voltage
VIL
—MVREF – 0.45
V
AC input high voltage
VIH
MVREF + 0.45
V
Table 17. DDR2 SDRAM Input AC Timing Specifications
At recommended operating conditions. with GVDD of 1.8± 100 mV
Parameter
Symbol
Min
Max
Unit
Notes
Controller skew for MDQS—MDQ/MECC @266 MHz
tCISKEW
–875
875
ps
1, 2,3
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ or MECC signal is called tDISKEW. This can
be determined by the following equation: tDISKEW = +/–(T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is
the absolute value of tCISKEW.
3. Memory controller ODT value of 150
Ω is recommended
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