參數(shù)資料
型號(hào): MPC8308CZQAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, MAPBGA-473
文件頁(yè)數(shù): 53/88頁(yè)
文件大?。?/td> 2550K
代理商: MPC8308CZQAGD
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Freescale Semiconductor
57
I
2C
Figure 45 provides the AC test load for the I2C.
Figure 45. I2C AC Test Load
Figure 46 shows the AC timing diagram for the I2C bus.
Figure 46. I2C Bus AC Timing Diagram
Setup time for STOP condition
tI2PVKH
0.6
μs
Bus free time between a STOP and START condition
tI2KHDX
1.3
μs
Noise margin at the LOW level for each connected device (including hysteresis)
VNL
0.1
× NVDD
—V
Noise margin at the HIGH level for each connected device (including hysteresis)
VNH
0.2
× NVDD
—V
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH symbolizes I
2C timing (I2)
with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock reference (K) going to the high
(H) state or setup time. Also, tI2SXKL symbolizes I
2C timing (I2) for the time that the data with respect to the start condition (S)
went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time. Also, tI2PVKH symbolizes I
2C timing
(I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the tI2C clock reference
(K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
2. The device provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DXKL has only to be met if the device does not stretch the low period (tI2CL) of the SCL signal.
4. CB = capacitance of one bus line in pF.
5. The device does not follow the
I2C-BUS Specifications, Version 2.1, regarding the tI2CF AC parameter.
Table 44. I2C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 43).
Parameter
Symbol1
Min
Max
Unit
Output
Z0 = 50 Ω
NVDD/2
RL = 50 Ω
Sr
S
SDA
SCL
tI2CF
tI2SXKL
tI2CL
tI2CH
tI2DXKL
tI2DVKH
tI2SXKL
tI2SVKH
tI2KHKL
tI2PVKH
tI2CR
tI2CF
PS
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