參數(shù)資料
型號(hào): MPC8308CZQAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, MAPBGA-473
文件頁數(shù): 78/88頁
文件大小: 2550K
代理商: MPC8308CZQAGD
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
8
Freescale Semiconductor
RESET Initialization
4.2
AC Electrical Characteristics
The primary clock source for the device is SYS_CLK_IN. Table 8 provides the system clock input
(SYS_CLK_IN) AC timing specifications for the device.
Table 9. RTC_PIT_CLOCK AC Timing Specifications
5
RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the device.
5.1
RESET DC Electrical Characteristics
Table 10 provides the DC electrical characteristics for the RESET pins.
Table 8. SYS_CLK_IN AC Timing Specifications
Parameter
Symbol
Min
Typ
Max
Unit
Notes
SYS_CLK_IN frequency
fSYS_CLK_IN
24
66.67
MHz
1, 6
SYS_CLK_IN period
tSYS_CLK_IN
15
41.67
ns
SYS_CLK_IN rise and fall time
tKH, tKL
0.6
1.2
ns
2
SYS_CLK_IN duty cycle
tKHK/tSYS_CLK_IN
40
60
%
3
SYS_CLK_IN Jitter
±150
ps
4, 5
Notes:
1. Caution: The system and core must not exceed their respective maximum or minimum operating frequencies.
2. Rise and fall times for SYS_CLK_IN are measured at 0.4 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread @ 33 kHz (max rate).
Parameter
Symbol
Min
Typ
Max
Unit
Notes
RTC_PIT_CLOCK frequency
fRTC_PIT_CLOCK
1
32768
Hz
RTC_PIT_CLOCK rise and fall time
tRTCH, tRTCL
1.5
3
μs—
RTC_PIT_CLOCK duty cycle
tRTCHK/tRTC_PIT_CLO
CK
45
55
%
Table 10. RESET Pins DC Electrical Characteristics
Characteristic
Symbol
Condition
Min
Max
Unit
Input high voltage
VIH
—2.0
NVDD +0.3
V
Input low voltage
VIL
–0.3
0.8
V
Input current
IIN
0 V
≤ VIN ≤ NVDD
±5
μA
Output high voltage
VOH
IOH = –8.0 mA
2.4
V
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