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參數(shù)資料
| 型號： | MPC8308CZQAGD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473 |
| 封裝： | 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, MAPBGA-473 |
| 文件頁數(shù)： | 50/88頁 |
| 文件大?。?/td> | 2550K |
| 代理商： | MPC8308CZQAGD |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
54
Freescale Semiconductor
JTAG
Figure 40 provides the AC test load for TDO and the boundary-scan outputs.
Figure 40. AC Test Load for the JTAG Interface
Figure 41 provides the JTAG clock input timing diagram.
Figure 41. JTAG Clock Input Timing Diagram
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
—
ns
5
JTAG external clock to output high impedance:
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
19
9
ns
5, 6
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in question.
The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see Figure 40).
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH symbolizes JTAG device
timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the tJTG clock reference (K)
going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect to the time data input signals
(D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note that, in general, the clock reference
symbol representation is based on three letters representing the clock of a particular functional. For rise and fall times, the
latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK.
5. Non-JTAG signal output timing with respect to tTCLK.
6. Guaranteed by design and characterization.
Table 42. JTAG AC Timing Specifications (Independent of SYS_CLK_IN) 1 (continued)
At recommended operating conditions (see Table 2).
Parameter
Symbol2
Min
Max
Unit
Notes
Output
Z0 = 50 Ω
NVDD/2
RL = 50 Ω
JTAG
tJTKHKL
tJTGR
External Clock
VM
tJTG
tJTGF
VM = Midpoint Voltage (NVDD/2)
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相關代理商/技術參數(shù) |
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| MPC8308CZQAGDA | 功能描述:微處理器 - MPU E300 EXT TEMP PB 400 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8308-KIT | 功能描述:開發(fā)板和工具包 - 其他處理器 For MPC8308 Ethernet USB I2C SPI RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8308-NSG | 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8308-NSG RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8308-NSG | 制造商:Freescale Semiconductor 功能描述:MPC8308-NSG*NIC* |
| MPC8308-RDB | 功能描述:開發(fā)板和工具包 - 其他處理器 Refer. Board MPC8308 RoHS:否 制造商:Freescale Semiconductor 產品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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