參數(shù)資料
型號(hào): MPC8308CZQAGD
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473
封裝: 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, MAPBGA-473
文件頁(yè)數(shù): 75/88頁(yè)
文件大小: 2550K
代理商: MPC8308CZQAGD
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
Freescale Semiconductor
77
Clocking
Table 55 provides the operating frequencies for the device under recommended operating conditions
21.2
System PLL Configuration
The system PLL is controlled by the RCWL[SPMF] parameter. Table 56 shows the multiplication factor
encodings for the system PLL.
As described in Section 21, “Clocking,the LBCM, DDRCM, and SPMF parameters in the reset
configuration word low select the ratio between the primary clock input (SYS_CLK_IN) and the internal
Table 55. Operating Frequencies for MPC8308
Characteristic1
Maximum Operating Frequency
Unit
e300 core frequency (
core_clk)
400
MHz
Coherent system bus frequency (
csb_clk)
133
MHz
DDR2 memory bus frequency (MCK)2
133
MHz
Local bus frequency (LCLK
0)3
66
MHz
Notes:
1. The SYS_CLK_IN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting
csb_clk,
MCK, LCLK0, and
core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the
lbc_clk frequency (depending on LCCR[CLKDIV]) which is in turn, 1x or 2x
the
csb_clk frequency (depending on RCWL[LBCM]).
Table 56. System PLL Ratio
RCWL[SPMF]
csb_clk : SYS_CLK_IN
0000
Reserved
0001
Reserved
0010
2 : 1
0011
3 : 1
0100
4 : 1
0101
5 : 1
0110–1111
Reserved
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MPC8308-RDB 功能描述:開(kāi)發(fā)板和工具包 - 其他處理器 Refer. Board MPC8308 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評(píng)估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: