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參數(shù)資料
| 型號： | MPC8308CZQAGD |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 266 MHz, MICROPROCESSOR, PBGA473 |
| 封裝： | 19 X 19 MM, 0.80 MM PITCH, 1.39 MM HEIGHT, MAPBGA-473 |
| 文件頁數(shù)： | 81/88頁 |
| 文件大?。?/td> | 2550K |
| 代理商： | MPC8308CZQAGD |
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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 1
82
Freescale Semiconductor
System Design Information
23.1
System Clocking
The device includes two PLLs.
1. The platform PLL generates the platform clock from the externally supplied SYS_CLK_IN input.
The frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL
ratio configuration bits as described in Section 21.2, “System PLL Configuration.”
2. The e300 core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e300 core clock and the platform clock is selected using the e300 PLL ratio
configuration bits as described in Section 21.3, “Core PLL Configuration.”
23.2
PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AVDD1 for
core PLL and AVDD2 for the platform PLL). The AVDD level should always be equivalent to VDD, and
preferably these voltages are derived directly from VDD through a low-pass filter scheme such as the
following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide independent filter circuits as illustrated in Figure 54, one to each of the two AVDD pins. By
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs’ resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum effective series inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AVDD
pin, which is on the periphery of package, without the inductance of vias.
Figure 54 shows the PLL power supply filter circuits.
Figure 54. PLL Power Supply Filter Circuit
23.3
Decoupling Recommendations
Due to large address and data buses and high-operating frequencies, the device can generate transient
power surges and high-frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8308 system, and the MPC8308
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each VDD, NVDD, GVDD, and LVDD pin of the device.
VDD
AVDD1 and AVDD2
2.2 F
Low ESL Surface Mount Capacitors
10
Ω
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MPC8308CZQAGDA | 功能描述:微處理器 - MPU E300 EXT TEMP PB 400 RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MPC8308-KIT | 功能描述:開發(fā)板和工具包 - 其他處理器 For MPC8308 Ethernet USB I2C SPI RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8308-NSG | 功能描述:開發(fā)板和工具包 - 其他處理器 MPC8308-NSG RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
| MPC8308-NSG | 制造商:Freescale Semiconductor 功能描述:MPC8308-NSG*NIC* |
| MPC8308-RDB | 功能描述:開發(fā)板和工具包 - 其他處理器 Refer. Board MPC8308 RoHS:否 制造商:Freescale Semiconductor 產(chǎn)品:Development Systems 工具用于評估:P3041 核心:e500mc 接口類型:I2C, SPI, USB 工作電源電壓: |
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