
41
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
............................................-1V to +3.6V
Voltage on V
DD
Q Supply
Relative to V
SS
............................................-1V to +3.6V
Voltage on V
REF
and Inputs
Relative to V
SS
............................................-1V to +3.6V
Voltage on I/O Pins
Relative to V
SS
...............................-0.5V to V
DD
Q +0.5V
Operating Temperature, T
A
(ambient) ...0°C to +70°C
Storage Temperature (plastic) ............-55°C to +150°C
Power Dissipation ........................................................ 2W
Short Circuit Output Current................................. 50mA
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
AC INPUT OPERATING CONDITIONS
(Notes: 1-5, 14, 16, 40; notes appear on pages 46-49) (0°C
≤
T
A
≤
+70°C; V
DD
= +2.5V ±0.125V, V
DD
Q = +2.5V ±0.125V)
PARAMETER/CONDITION
Input High (Logic 1) Voltage; DQ
Input Low (Logic 0) Voltage; DQ
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
SYMBOL
V
IH
(
AC
)
V
IL
(
AC
)
V
ID
(
AC
)
V
IX
(
AC
)
MIN
MAX
–
UNITS
V
V
V
V
NOTES
14, 28, 39
14, 28, 39
8
9
V
REF
+ 0.310
–
0.7
0.5xV
DD
Q-0.2
V
REF
- 0.310
V
DD
Q + 0.6
0.5xV
DD
Q+0.2
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1-5, 16, 40; notes appear on pages 46-49) (0°C
≤
T
A
≤
+70°C; V
DD
= +2.5V ±0.125V, V
DD
Q = +2.5V ±0.125V)
PARAMETER/CONDITION
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
Clock Input Voltage Level; CK and CK#
Clock Input Differential Voltage; CK and CK#
Clock Input Crossing Point Voltage; CK and CK#
INPUT LEAKAGE CURRENT
Any input 0V
≤
V
IN
≤
V
DD
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V
≤
V
OUT
≤
V
DD
Q)
OUTPUT LEVELS: Impedance Match
High Current (V
OUT
= V
DD
Q-0.373V, minimum V
REF
, minimum V
TT
)
Low Current (V
OUT
= 0.373V, maximum V
REF
,maximum V
TT
)
OUTPUT LEVELS: Reduced drive option -
High Current (V
OUT
= V
DD
Q-0.763V, minimum V
REF
, minimum V
TT
)
Low Current (V
OUT
= 0.763V, maximum V
REF
,maximum V
TT
)
SYMBOL
V
DD
V
DD
Q
V
REF
V
TT
V
IH
(
DC
)
V
IL
(
DC
)
V
IN
V
ID
V
IX
MIN
2.375
2.375
MAX
2.625
2.625
UNITS NOTES
V
V
V
V
V
V
V
V
V
40
6
7
28
28
0.49
x
V
DD
Q
V
REF
- 0.04
V
REF
+ 0.15
-0.3
-0.3
0.36
1.15
0.51
x
V
DD
Q
V
REF
+ 0.04
V
DD
+ 0.3
V
REF
- 0.15
V
DD
Q + 0.3
V
DD
Q + 0.6
1.35
8
9
I
I
-2
2
μA
I
OZ
-5
5
μA
I
OH
I
OL
-4
4
–
–
mA
mA
37, 39
I
OHR
I
OLR
-9
9
–
–
mA
mA
38, 39