
6
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
38, 39, 40, 41, 42, 43, 44
87, 88, 90
91
93
52
NC
–
No Connect: These pins should be left unconnected.
DNU
NC/RFU
NC (MCL)
–
Do Not Use: Must float to minimize noise.
Reserved for Future Use
No Connect: Not internally connected. Must Connect LOW (for
compatibility with SGRAM devices).
DQ Power Supply: +2.5V ±0.125V. Isolated on the die for
improved noise immunity. 1.8V option
DQ Ground. Isolated on the die for improved noise immunity.
2, 8, 14, 22, 59, 67, 73,
79, 86, 95
5, 11, 19, 62, 70, 76,
82, 92, 99
15, 35, 65, 96
16, 46, 66, 85
58
V
DD
Q
Supply
V
SS
Q
Supply
V
DD
V
SS
V
REF
Supply
Supply
Supply
Power Supply: +2.5V ±0.125V.
Ground.
SSTL_2 reference voltage.
PIN DESCRIPTIONS (continued)
TQFP PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
NOTE:
1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins
deemed to be of importance.
FBGA BALLOUT
DQS0
DM0
VSSQ
V
SS
Q
DQ21
DQ10
V
DD
Q
DQ15
DQ16
V
SS
DQ26
V
DD
V
DD
Q
V
DD
Q
DQ4
DQ3
V
SS
Q
DM2
DM1
DQS2
DQS1
DQ22
DQ8
V
SS
Q
V
SS
Q
NC
V
DD
Q
DQ1
DQ6
DQ2
A2
DQ0
V
DD
Q
CS#
V
DD
Q
DQ31
V
DD
Q
DQ30
V
SS
Q
DQ29
DSF/MCL
DQ24
DQ7
V
SS
Q
DQ28
VSSQ
DM3
DQS3
DQ27
DQ5
NC
V
SS
Q
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
V
SS
Q
V
SS
Q
DQ25
A
B
C
D
E
F
G
H
J
K
L
M
V
DD
Q
V
DD
V
DD
Q
V
SS
V
SS
Q
V
SS
V
SS
V
SS
A11
A3
A4
A9
A5
CK#
V
DD
CKE
V
DD
V
SS
V
SS
Q
V
SS
Q
V
SS
V
SS
Q
RFU
CAS#
V
DD
Q
V
DD
DQ17
V
SS
Q
DQ14
V
DD
Q
RAS#
DQ19
DQ18
V
DD
Q
V
SS
Q
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
SS
/
θ
1
V
DD
Q
NC
DQ20
DQ23
WE#
NC
NC
V
DD
Q
V
DD
NC
BA0
V
SS
Q
V
SS
BA1
A0
V
SS
V
SS
Q
V
SS
Q
DQ13
DQ12
NC
V
DD
Q
DQ11
V
DD
Q
DQ9
V
REF
A1
A6
A7
A8/AP
NC
NC
CK
V
SS
RFU
V
DD
A10
3
2
NOTE:
1. This package uses 4 DQS lines