參數(shù)資料
型號(hào)： MT46V4M32
廠商： Micron Technology, Inc.
英文描述： DOUBLE DATA RATE DDR SDRAM
中文描述： 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存
文件頁(yè)數(shù)： 38/66頁(yè)
文件大小： 1921K
代理商： MT46V4M32
38
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
NOTE (continued):
5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be
applied on each positive clock edge during these states.
Refreshing: Starts with registration of an AUTO REFRESH command and ends when
t
RC is met.
Once
t
RC is met, the DDR SDRAM will be in the all banks idle state.
Accessing Mode
Register: Starts with registration of a LOAD MODE REGISTER command and ends when
t
MRD
has been met. Once
t
MRD is met, the DDR SDRAM will be in the all banks idle state.
Precharging All: Starts with registration of a PRECHARGE ALL command and ends when
t
RP is met.
Once
t
RP is met, all banks will be in the idle state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.
8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank.
10. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or
WRITEs with auto precharge disabled.
11. Requires appropriate DM masking.
12. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to
end the READ burst prior to asserting a WRITE command.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT46V4M32LG 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM
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