- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385639 > MT46V4M32 (Micron Technology, Inc.) DOUBLE DATA RATE DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | MT46V4M32 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | DOUBLE DATA RATE DDR SDRAM |
| 中文描述： | 雙倍數(shù)據(jù)速率的DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 47/66頁 |
| 文件大?。?/td> | 1921K |
| 代理商： | MT46V4M32 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁當(dāng)前第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
47
128Mb: x32 DDR SDRAM
4M32DDR_B.p65 – Rev. B, Pub. 7/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
DDR SDRAM
ADVANCE
24. The I/O capacitance per DQS and DQ byte/group
will not differ by more than this maximum
amount for any given device.
25. The valid data window is derived by achieving
other specifications -
t
HP (
t
CK/2),
t
DQSQ,
and
t
QH [
t
HP - 0.4ns (-3),
t
HP - 0.4ns (-4) or
t
HP -
0.5ns (-4)]. The data valid window derates
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle
variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: DQS with DQ0-
DQ31
27. This limit is actually a nominal value and does
not result in a fail value. CKE is HIGH during
REFRESH command period (
t
RFC [MIN]) else
CKE is LOW (i.e., during standby).
28. The DC values define where the input slew rate
requirements are imposed, and the input signal
must not violate these levels in order to maintain
NOTES (continued)
a valid level. The inputs require the AC value to
be achieved during signal transition edge and
the driver should achieve the same slew rate
through the AC values.
29. The Input capacitance per pin group will not
differ by more than this maximum amount for
any given device..
30. CK and CK# input slew rate must be
≥
1V/ns.
31. DQ and DM input slew rates must not deviate
from DQS by more than 10%. If the DQ/DM/DQS
slew rate is less than 0.5V/ns, timing is no longer
referenced to the mid-point but to the V
IL
(
AC
)
maximum and V
IH
(
AC
) minimum points.
32. Vdd must not vary more than 4% if CKE is not
active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
34.
t
HP (MIN) is the lesser of
t
CL minimum and
t
CH
minimum actually applied to the device CK and CK/
inputs, collectively during bank active.
DERATING DATA VALID WINDOW
(
t
QH -
t
DQSQ)
t
0.850
0.834
0.817
0.801
0.784
0.768
0.751
0.735
0.718
0.702
0.685
1.150
1.130
1.110
1.090
1.070
1.050
1.030
1.010
0.990
0.970
0.950
1.500
1.475
1.450
1.425
1.400
1.375
1.350
1.325
1.300
1.275
1.250
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
50/50
49.5/50.5
49/51
48.5/52.5
48/52
47.5/53.5
47/53
46.5/54.5
46/54
45.5/55.5
45/55
Clock Duty Cycle
n
-33 @ tCK = 3.3ns
-4 @ tCK = 4ns
-5 @ tCK = 5ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT46V4M32LG | I.MX31 LITE KIT |
| MT46V64M4 | 16 Meg x 4 x 4 banks DDR SDRAM(16M x 4 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM) |
| MT46V64M8 | 16 Meg x 8 x 4 banks DDR SDRAM(16M x 8 x 4組,雙數(shù)據(jù)速率同步動態(tài)RAM) |
| MT48LC16M8A1TG | SYNCHRONOUS DRAM |
| MT48LC32M4A1 | ECONOLINE: RSZ/P - 1kVDC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT46V4M32LG | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE DDR SDRAM |
| MT46V64M16 | 制造商:MICRON 制造商全稱:Micron Technology 功能描述:DOUBLE DATA RATE (DDR) SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。