參數(shù)資料
型號(hào)： MT48LC4M16A2F4-6IT:G
元件分類(lèi)： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁(yè)數(shù)： 24/72頁(yè)
文件大小： 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
30
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
An example is shown in Figure 20 on page 31. Data n + 1 is either the last of a burst of two
or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a prefetch architecture. A WRITE
command can be initiated on any clock cycle following a previous WRITE command.
Full-speed random write accesses within a page can be performed to the same bank, as
shown in Figure 21 on page 32, or each subsequent WRITE may be performed to a
different bank.
Figure 18:
WRITE Command
Figure 19:
WRITE Burst
Note:
NOTE: BL = 2. DQM is LOW.
DON’T CARE
VALID ADDRESS
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A10
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A0–A9: x4
A0–A8: x8
A0–A7: x16
A11: x4
A9, A11: x8
A8, A9, A11: x16
BA0, BA1
BANK
ADDRESS
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
DON’T CARE
WRITE
DIN
n + 1
NOP
BANK,
COL n
TRANSITIONING DATA
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MT48LC4M16A2F4-75 制造商:Micron Technology Inc 功能描述:
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