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參數(shù)資料
| 型號： | MT48LC4M16A2F4-6IT:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 33/72頁 |
| 文件大?。?/td> | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
39
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Figure 32:
WRITE With Auto Precharge Interrupted by a WRITE
Notes:
1. DQM is LOW.
Notes:
1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous
clock edge.
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of
COMMANDn.
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for
clock edge n + 1 (provided that tCKS is met).
6. Exiting self refresh at clock edge n will put the device in the all banks idle state after tXSR is
met. COMMAND INHIBIT or NOP commands should be issued on any clock edges occurring
during the tXSR period. A minimum of two NOP commands must be provided during tXSR
period.
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize
the next command at clock edge n + 1.
Table 8:
Truth Table 2 – CKE
Notes 1–4 apply to entire table
CKEn-1
CKEn
Current State
COMMANDn
ACTIONn
Notes
L
Power-Down
X
Maintain power-down
Self refresh
X
Maintain self refresh
Clock suspend
X
Maintain clock suspend
L
H
Power-Down
COMMAND INHIBIT or NOP
Exit power-down
Self refresh
COMMAND INHIBIT or NOP
Exit self refresh
Clock suspend
X
Exit clock suspend
H
L
All banks idle
COMMAND INHIBIT or NOP
Power-Down entry
All banks idle
AUTO REFRESH
Self refresh entry
Reading or writing
WRITE or NOP
Clock suspend entry
H
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
d + 1
DIN
d
DIN
a + 1
DIN
a + 2
DIN
a
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
NOP
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
WRITE with Burst of 4
Write-Back
WR - BANK n
tRP - BANK n
t WR - BANK m
TRANSITIONING DATA
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|---|---|
| MT48LC4M16A2F4-75 | 制造商:Micron Technology Inc 功能描述: |
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