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參數(shù)資料
| 型號： | MT48LC4M16A2F4-6IT:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 3/72頁 |
| 文件大小： | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
11
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Pin/Ball Assignments and Descriptions
Table 4:
Pin/Ball Descriptions
TSOP Pin
Numbers
VFBGA
Ball
Numbers
Symbol
Type
Description
38
F2
CLK
Input
Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.
37
F3
CKE
Input
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK
signal. Deactivating the clock provides PRECHARGE power-down and
SELF REFRESH operation (all banks idle), ACTIVE power-down (row
active in any bank), or CLOCK SUSPEND operation (burst/access in
progress). CKE is synchronous except after the device enters power-
down and self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CLK, are
disabled during power-down and self refresh modes, providing low
standby power. CKE may be tied HIGH.
19
G9
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when CS# is
registered HIGH, but READ/WRITE bursts already in progress will
continue and DQM will retain its DQ mask capability while CS#
remains HIGH. CS# provides for external bank selection on systems
with multiple banks. CS# is considered part of the command code.
16, 17, 18
F9, F7, F8
WE#, CAS#,
RAS#
Input
Command inputs: WE#, CAS#, and RAS# (along with CS#) define the
command being entered.
39
–
x4, x8:
DQM
Input
Input/output mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC
and DQMH is DQM. On the x16, DQML corresponds to DQ0–DQ7 and
DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered
same state when referenced as DQM.
15, 39
E8, F1
x16:
DQML,
DQMH
20, 21
G7, G8
BA0, BA1
Input
Bank address inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
23–26,
29–34, 22,
35
H7, H8, J8,
J7, J3, J2,
H3, H2, H1,
G3, H9, G2
A0–A11
Input
Address inputs: A0–A11 are sampled during the ACTIVE command
(row-address A0–A11) and READ/WRITE command (column-address
A0–A9 [x4]; A0–A8 [x8]; A0–A7 [x16]; with A10 defining auto
precharge) to select one location out of the memory array in the
respective bank. A10 is sampled during a precharge command to
determine whether all banks are to be precharged (A10[HIGH]) or
bank selected by BA0, BA1 (A1[LOW]). The address inputs also provide
the op-code during a LOAD MODE REGISTER command.
2, 4, 5, 7, 8,
10, 11, 13,
42, 44, 45,
47, 48, 50,
51, 53
A8, B9, B8,
C9, C8, D9,
D8, E9, E1,
D2, D1, C2,
C1, B2, B1,
A2
DQ0–DQ15
x16: I/O
Data input/output: Data bus for x16 (4, 7, 10, 13, 42, 45, 48, and 51 are
NCs for x8; and 2, 4, 7, 8, 10, 13, 42, 45, 47, 48, 51, and 53 are NCs for
x4).
2, 5, 8, 11,
44, 47, 50,
53
–
DQ0–DQ7
x8: I/O
Data input/output: Data bus for x8 (2, 8, 47, 53 are NCs for x4).
5, 11, 44,
50
–
DQ0–DQ3
x4: I/O
Data input/output: Data bus for x4.
40
E2
NC
–
No connect: These pins should be left unconnected.
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| MT48LC4M16A2F4-75 | 制造商:Micron Technology Inc 功能描述: |
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