參數(shù)資料
型號(hào)： MT48LC4M16A2F4-6IT:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁數(shù)： 29/72頁
文件大小： 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
35
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Figure 26:
Power-Down
Clock Suspend
The clock suspend mode occurs when a column access/burst is in progress and CKE is
registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing”
the synchronous logic.
For each positive clock edge on which CKE is sampled LOW, the next internal positive
clock edge is suspended. Any command or data present on the input pins at the time of a
suspended internal clock edge is ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as long as the clock is suspended. (See
examples in Figures 27 and 28 on page 36.)
Clock suspend mode is exited by registering CKE HIGH; the internal clock and related
operation will resume on the subsequent positive clock edge.
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed burst
length. READ commands access columns according to the programmed burst length
and sequence, just as in the normal mode of operation (M9 = 0).
DON’T CARE
tRAS
tRCD
tRC
All banks idle
Input buffers gated off
Exit power-down mode.
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tCKS
> tCKS
COMMAND
NOP
ACTIVE
Enter power-down mode.
NOP
CLK
CKE
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參數(shù)描述
MT48LC4M16A2F4-75 制造商:Micron Technology Inc 功能描述:
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