參數(shù)資料
型號： MT48LC4M16A2F4-6IT:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
封裝： 8 X 8 MM, VFBGA-54
文件頁數(shù)： 52/72頁
文件大小： 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
56
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Timing Diagrams
Figure 39:
Self Refresh Mode
Notes:
1. No maximum time limit for self refresh mode. tRAS(MAX) applies to non-self refresh mode.
2. tXSR requires minimum of two clocks regardless of frequency and timing.
3. Self refresh mode not supported on automotive temperature (AT) devices.
tCH
tCL
tCK
tRP
CKE
CLK
DQ
Enter self refresh mode
Precharge all
active banks
tXSR2
CLK stable prior to exiting
self refresh mode
Exit self refresh mode
(Restart refresh time base)
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DON’T CARE
COMMAND
tCMH
tCMS
AUTO
REFRESH
PRECHARGE
NOP
or COMMAND
INHIBIT
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BA0, BA1
BANK(S)
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High-Z
tCKS
AH
AS
AUTO
REFRESH
tRAS(MIN)1
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tCKH
tCKS
DQM/
DQML, DQMH
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t
A0–A9, A11
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ALL BANKS
SINGLE BANK
A10
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T0
T1
T2
Tn + 1
To + 1
To + 2
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≥
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參數(shù)描述
MT48LC4M16A2F4-75 制造商:Micron Technology Inc 功能描述:
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