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| 型號： | MT48LC4M16A2F4-6IT:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54 |
| 封裝： | 8 X 8 MM, VFBGA-54 |
| 文件頁數(shù)： | 32/72頁 |
| 文件大?。?/td> | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
38
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Figure 30:
READ With Auto Precharge Interrupted by a WRITE
Notes:
1. DQM is HIGH at T2 to prevent DOUT a +1 from contending with DIN d at T4.
Figure 31:
WRITE With Auto Precharge Interrupted by a READ
Notes:
1. DQM is LOW.
CLK
DQ
DOUT
a
T2
T1
T4
T3
T6
T5
T0
COMMAND
NOP
DIN
d + 1
DIN
d
DIN
d + 2
DIN
d + 3
NOP
T7
BANK n
BANK m
ADDRESS
Idle
NOP
DQM
BANK n,
COL a
BANK m,
COL d
WRITE - AP
BANK m
Internal
States
t
Page
Active
READ with Burst of 4
Interrupt Burst, Precharge
Page Active
WRITE with Burst of 4
Write-Back
RP - BANK n
t WR - BANK m
CAS Latency = 3 (BANK n)
READ - AP
BANK n
1
DON’T CARE
TRANSITIONING DATA
DON’T CARE
CLK
DQ
T2
T1
T4
T3
T6
T5
T0
COMMAND
WRITE - AP
BANK n
NOP
DIN
a + 1
DIN
a
NOP
T7
BANK n
BANK m
ADDRESS
BANK n,
COL a
BANK m,
COL d
READ - AP
BANK m
Internal
States
t
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
Page Active
READ with Burst of 4
t
tRP - BANK m
DOUT
d
DOUT
d + 1
CAS Latency = 3 (BANK m)
RP - BANK n
WR - BANK n
TRANSITIONING DATA
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| MT48LC4M16A2F4-75 | 制造商:Micron Technology Inc 功能描述: |
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