- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄45322 > MT80C51T-36D (TEMIC SEMICONDUCTORS) 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 PDF資料下載
參數(shù)資料
| 型號(hào)： | MT80C51T-36D |
| 廠(chǎng)商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 125/189頁(yè) |
| 文件大小： | 4133K |
| 代理商： | MT80C51T-36D |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)當(dāng)前第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)
58
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
clock cycles. Note that the input of the noise canceler and edge detector is always enabled unless the Timer/Coun-
ter is set in a Waveform Generation mode that uses ICR0 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP0 pin.
11.5.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The noise canceler input is
monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge
detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC0) bit in Timer/Counter Control
Register B (TCCR0B). When enabled the noise canceler introduces additional four system clock cycles of delay
from a change applied to the input, to the update of the ICR0 Register. The noise canceler uses the system clock
and is therefore not affected by the prescaler.
11.5.3
Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity for handling the
incoming events. The time between two events is critical. If the processor has not read the captured value in the
ICR0 Register before the next event occurs, the ICR0 will be overwritten with a new value. In this case the result of
the capture will be incorrect.
When using the Input Capture interrupt, the ICR0 Register should be read as early in the interrupt handler routine
as possible. Even though the Input Capture interrupt has relatively high priority, the maximum interrupt response
time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during
operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture.
Changing the edge sensing must be done as early as possible after the ICR0 Register has been read. After a
change of the edge, the Input Capture Flag (ICF0) must be cleared by software (writing a logical one to the I/O bit
location). For measuring frequency only, the clearing of the ICF0 flag is not required (if an interrupt handler is
used).
11.6
Output Compare Units
The 16-bit comparator continuously compares TCNT0 with the Output Compare Register (OCR0x). If TCNT equals
OCR0x the comparator signals a match. A match will set the Output Compare Flag (OCF0x) at the next timer clock
cycle. If enabled (OCIE0x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF0x flag
is automatically cleared when the interrupt is executed. Alternatively the OCF0x flag can be cleared by software by
writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output
according to operating mode set by the Waveform Generation mode (WGM03:0) bits and Compare Output mode
(COM0x1:0) bits. The TOP and BOTTOM signals are used by the Waveform Generator for handling the special
cases of the extreme values in some modes of operation (“Modes of Operation” on page 61).
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e., counter resolu-
tion). In addition to the counter resolution, the TOP value defines the period time for waveforms generated by the
Waveform Generator.
Figure 11-6 on page 59 shows a block diagram of the Output Compare unit. The small “n” in the register and bit
names indicates the device number (n = 0 for Timer/Counter 0), and the “x” indicates Output Compare unit (A/B).
The elements of the block diagram that are not directly a part of the Output Compare unit are gray shaded.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MS80C31-12R | 8-BIT, 12 MHz, MICROCONTROLLER, PQCC44 |
| MT80C51C-12D | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| MS80C31-20R | 8-BIT, 20 MHz, MICROCONTROLLER, PQCC44 |
| MV80C51T-16D | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| MP80C31-30D | 8-BIT, 30 MHz, MICROCONTROLLER, PDIP40 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT80GB | 制造商:Datak Corporation 功能描述: |
| MT80JSF1G72NDY-1G1F1A2 | 制造商:Micron Technology Inc 功能描述:8GB 1GX72 DDR3 SDRAM MODULE PBF DIMM 1.5V REGISTERED - Trays |
| MT80KSF1G72NDY-1G4F1A3 | 制造商:Micron Technology Inc 功能描述:8GB 1GX72 DDR3 SDRAM MODULE PBF DIMM 1.35V FULLY BUFFERED - Trays |
| MT810 | 制造商:MARKTECH 制造商全稱(chēng):Marktech Corporate 功能描述:STANDARD T-1 3/4 LED LAMPS |
| MT-8100 | 制造商:Eclipse Tools 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。