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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 138/189頁 |
| 文件大小： | 4133K |
| 代理商： | MT80C51T-36D |
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7
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
Six of the 16 registers can be used as three 16-bit indirect address register pointers for data space addressing –
enabling efficient address calculations. One of the these address pointers can also be used as an address pointer
for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register,
described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single
register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated
to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, capable of directly addressing
the whole address space. Most AVR instructions have a single 16-bit word format but 32-bit wide instructions also
exist. The actual instruction set varies, as some devices only implement a part of the instruction set.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the SRAM size
and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or
interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can
easily be accessed through the four different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in
the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have
priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the
priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other
I/O functions. The I/O memory can be accessed as the data space locations, 0x0000 - 0x003F.
4.2
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 16 general purpose working registers.
Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an
immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-
functions. Some implementations of the architecture also provide a powerful multiplier supporting both
signed/unsigned multiplication and fractional format. See document “AVR Instruction Set” and section “Instruction
Set Summary” on page 150 for a detailed description.
4.3
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This
information can be used for altering program flow in order to perform conditional operations. Note that the Status
Register is updated after all ALU operations, as specified in document “AVR Instruction Set” and section “Instruc-
tion Set Summary” on page 150. This will in many cases remove the need for using the dedicated compare
instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and restored when returning
from an interrupt. This must be handled by software.
4.4
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required perfor-
mance and flexibility, the following input/output schemes are supported by the Register File:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
One 16-bit output operand and one 16-bit result input
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