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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 135/189頁 |
| 文件大?。?/td> | 4133K |
| 代理商： | MT80C51T-36D |
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67
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represent special cases when generating a PWM waveform output in
the phase correct PWM mode. If the OCR0x is set equal to BOTTOM the output will be continuously low and if set
equal to TOP the output will be continuously high for non-inverted PWM mode. For inverted PWM the output will
have the opposite logic values.
11.8.5
Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM03:0
= 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase
and frequency correct PWM mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Com-
pare Output mode, the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x
while upcounting, and set on the compare match while downcounting. In inverting Compare Output mode, the
operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the sin-
gle-slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are
preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the
OCR0x Register is updated by the OCR0x Buffer Register, (see Figure 11-10 on page 66 and Figure 11-11 on
page 68).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR0 or OCR0A.
The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit
(ICR0 or OCR0A set to MAX). The PWM resolution in bits can be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the
value in ICR0 (WGM03:0 = 8), or the value in OCR0A (WGM03:0 = 9). The counter has then reached the TOP and
changes the count direction. The TCNT0 value will be equal to TOP for one timer clock cycle. The timing diagram
for the phase correct and frequency correct PWM mode is shown on Figure 11-11 on page 68. The figure shows
phase and frequency correct PWM mode when OCR0A or ICR0 is used to define TOP. The TCNT0 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes non-inverted
and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent compare matches
between OCR0x and TCNT0. The OC0x interrupt flag will be set when a compare match occurs.
R
PFCPWM
TOP
1
+
log
2
log
-----------------------------------
=
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