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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 133/189頁 |
| 文件大小： | 4133K |
| 代理商： | MT80C51T-36D |
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65
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
The PWM frequency for the output can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR0x Register represents special cases when generating a PWM waveform output in
the fast PWM mode. If the OCR0x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each
TOP+1 timer clock cycle. Setting the OCR0x equal to TOP will result in a constant high or low output (depending
on the polarity of the output set by the COM0x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0A to toggle
its logical level on each compare match (COM0A1:0 = 1). The waveform generated will have a maximum fre-
quency of f
0
A = fclk_I/O/2 when OCR0A is set to zero (0x0000). This feature is similar to the OC0A toggle in CTC
mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
11.8.4
Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM03:0 = 1, 2, 3, 10, or 11) provides a
high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, like the phase
and frequency correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOT-
TOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output
Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope
operation has lower maximum operation frequency than single slope operation. However, due to the symmetric
feature of the dual-slope PWM modes, these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or
OCR0A. The minimum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is
16-bit (ICR0 or OCR0A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
In phase correct PWM mode the counter is incremented until the counter value matches either one of the fixed val-
ues 0x00FF, 0x01FF, or 0x03FF (WGM03:0 = 1, 2, or 3), the value in ICR0 (WGM03:0 = 10), or the value in
OCR0A (WGM03:0 = 11). The counter has then reached the TOP and changes the count direction. The TCNT0
value will be equal to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown
on Figure 11-10 on page 66. The figure shows phase correct PWM mode when OCR0A or ICR0 is used to define
TOP. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes
represent compare matches between OCR0x and TCNT0. The OC0x interrupt flag will be set when a compare
match occurs.
f
OCnxPWM
f
clk_I/O
N1
TOP
+
-----------------------------------
=
R
PCPWM
TOP
1
+
log
2
log
-----------------------------------
=
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