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| 型號(hào)： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 91/189頁(yè) |
| 文件大?。?/td> | 4133K |
| 代理商： | MT80C51T-36D |
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27
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
8.
System Control and Reset
8.1
Resetting the AVR
During reset, all I/O registers are set to their initial values, and the program starts execution from the Reset Vector.
The instruction placed at the Reset Vector must be a RJMP – Relative Jump – instruction to the reset handling rou-
tine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code
can be placed at these locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of
the reset circuitry are defined in section “System and Reset Characteristics” on page 118.
Figure 8-1.
Reset Logic
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not
require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the
power to reach a stable level before normal operation starts. The start up sequence is described in “Starting from
8.2
Reset Sources
The ATtiny4/5/9/10 have three sources of reset:
Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V
POT)
External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum
pulse length
Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled
8.2.1
Power-on Reset
A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detection level is defined in sec-
tion “System and Reset Characteristics” on page 118. The POR is activated whenever V
CC is below the detection
level. The POR circuit can be used to trigger the Start-up Reset, as well as to detect a failure in supply voltage.
Reset Flag Register
(RSTFLR)
Delay Counters
CK
TIMEOUT
WDRF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
Watchdog
Oscillator
Power-on Reset
Circuit
VLM
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