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參數(shù)資料
| 型號： | MT80C51T-36D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁數(shù)： | 131/189頁 |
| 文件大?。?/td> | 4133K |
| 代理商： | MT80C51T-36D |
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63
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
not desirable. An alternative will then be to use the fast PWM mode using OCR0A for defining TOP (WGM03:0 =
15) since the OCR0A then will be double buffered.
For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical level on each
compare match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will
not be visible on the port pin unless the data direction for the pin is set to output (DDR_OC0A = 1). The waveform
generated will have a maximum frequency of
0
A = fclk_I/O/2 when OCR0A is set to zero (0x0000). The waveform fre-
quency is defined by the following equation:
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that the counter counts
from MAX to 0x0000.
11.8.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM03:0 = 5, 6, 7, 14, or 15) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM options by its single-slope operation.
The counter counts from BOTTOM to TOP then restarts from BOTTOM. In non-inverting Compare Output mode,
the Output Compare (OC0x) is cleared on the compare match between TCNT0 and OCR0x, and set at BOTTOM.
In inverting Compare Output mode output is set on compare match and cleared at BOTTOM. Due to the single-
slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct and
phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM
mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR0 or OCR0A. The mini-
mum resolution allowed is 2-bit (ICR0 or OCR0A set to 0x0003), and the maximum resolution is 16-bit (ICR0 or
OCR0A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of the fixed values
0x00FF, 0x01FF, or 0x03FF (WGM03:0 = 5, 6, or 7), the value in ICR0 (WGM03:0 = 14), or the value in OCR0A
(WGM03:0 = 15). The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 11-9 on page 64. The figure shows fast PWM mode when OCR0A or ICR0 is used
to define TOP. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the
TCNT0 slopes represent compare matches between OCR0x and TCNT0. The OC0x interrupt flag will be set when
a compare match occurs.
f
OCnA
f
clk_I/O
2 N
1
OCRnA
+
---------------------------------------------------
=
R
FPWM
TOP
1
+
log
2
log
-----------------------------------
=
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