參數(shù)資料
型號(hào)： NT5TU64M16DG-3C
廠商： NANYA TECHNOLOGY CORP
元件分類(lèi)： DRAM
英文描述： 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝： GREEN, BGA-84
文件頁(yè)數(shù)： 24/85頁(yè)
文件大小： 2622K
代理商： NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
30
REV 1.0
06 / 2010
Burst Read Command
The Burst Read command is initiated by having
and low while holding and high at the rising edge of the
clock. The address inputs determine the starting column address for the burst. The delay from the start of the command
until the data from the first cell appears on the outputs is equal to the value of the read latency (RL). The data strobe output
(DQS) is driven low one clock cycle before valid data (DQ) is driven onto the data bus. The first bit of the burst is
synchronized with the rising edge of the data strobe (DQS). Each subsequent data-out appears on the DQ pin in phase with
the DQS signal in a source synchronous manner. The RL is equal to an additive latency (AL) plus
latency (CL). The
CL is defined by the Mode Register Set (MRS).
The AL is defined by the Extended Mode Register Set (EMRS (1))
Basic Burst Read Timing
DQS,
DQS
DQ
DQS
t RPRE
t DQSQmax
tRPST
t DQSCK
tAC
Dout
CLK, CLK
CLK
t CH
tCL
t CK
DO-Read
t QH
DQSQmax
t
QH
t
t LZ
t HZ
Examples:
Burst Read Operation: RL = 5 (AL = 2, CL = 3, BL = 4)
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T8
Dout A0
Dout A1
Dout A2
Dout A3
RL = 5
AL = 2
CL = 3
NOP
<= tDQSCK
CMD
DQ
BRead523
DQS,
DQS
Post CAS
CK, CK
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NTA2410-10
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NTA2425-10
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NT5TU64M16GG-AC 制造商:Nanya Technology Corporation 功能描述:DRAM
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