參數(shù)資料
型號： NT5TU64M16DG-3C
廠商： NANYA TECHNOLOGY CORP
元件分類： DRAM
英文描述： 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝： GREEN, BGA-84
文件頁數(shù)： 65/85頁
文件大?。?/td> 2622K
代理商： NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
68
REV 1.0
06 / 2010
IDD Measurement Conditions
(VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V)
IDD1
Operating Current - One bank Active - Read - Precharge
IOUT = 0 mA; BL = 4, tCK = tCKmin, tRC = tRCmin; tRAS = tRASmin; tRCD = tRCDmin, CL = CLmin.;AL = 0; CKE is HIGH, CS is HIGH
between valid commands;Address bus inputs are SWITCHING,Data bus inputs are SWITCHING;
IDD2P
Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.; Other control and address inputs are STABLE, Data Bus inputs
are FLOATING.
IDD2N
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs are
SWICHTING; Data bus inputs are SWITCHING.
IDD2Q
Precharge Quiet Standby Current:All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING.
IDD3P(0)
Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE; Data Bus
inputs are FLOATING. MRS A12 bit is set to "0"( Fast Power-down Exit);
IDD3P(1)
Active Power-Down Current: All banks open; tCK = tCKmin.;CKE is LOW; Other control and address inputs are STABLE; Data Bus
inputs are FLOATING. MRS A12 bit is set to "1"( Slow Power-down Exit);
IDD3N
Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax.; tRP = tRPmin., CKE is HIGH; CS is HIGH between valid
commands; Other control and address inputs are SWITCHING; Data Bus inputs are SWITCHING.
IDD4R
Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax.,
tRP = tRPmin., CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data bus inputs are SWITCHING;
IOUT = 0mA.
IDD4W
Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax.,
tRP = tRPmin.;CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data Bus inputs are SWITCHING.
IDD5B
Burst Auto-Refresh Current:
tCK = tCKmin.; Refresh command every tRFC = tRFCmin interval; CKE is HIGH, CS is HIGH between
valid commands; Other control and adress inputs are SWITCHING; Data bus inputs are SWITCHING.
IDD6
Self-Refresh Current: CKE <= 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING; Data Bus inputs
are FLOATING.
IDD7
Operating Bank Interleave Read Current:
1. All bank interleaving reads; IOUT = 0 mA, BL =4, CL = CLmin., AL = tRCDmin. - 1*tCK; tCK = tCKmin., tRC = TRCmin.; tRRD = tRRDmin;
tRCD = 1*tCK, CKE = HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTS.
2. Timing pattern:
- DDR2 -667 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D
- DDR2 -800 5-5-5: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D D D D
- DDR2 -1066 6-6-6: A0 RA0 D D D D A1 RA1 D D D D A2 RA2 D D D D A3 RA3 D D D D D D D D D D
3. Legend : A=Activate, RA=Read with Auto-Precharge, D=DESELECT
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
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