
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
55
REV 1.0
06 / 2010
Operating Conditions
Absolute Maximum DC Ratings
Symbol
Parameter
Rating
Units
Notes
VDD
Voltage on VDD pin relative to VSS
-1.0
to + 2.3
V
1,3
VDDQ
Voltage on VDDQ pin relative to VSS
-0.5 to + 2.3
V
1,3
VDDL
Voltage on VDDL pin relative to VSS
-0.5 to + 2.3
V
1,3
VIN, VOUT
Voltage on any pin relative to VSS
-0.5 to + 2.3
V
1
TSTG
Storage Temperature
-55 to + 100
℃
1, 2
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3. When VDD, VDDQ, and VDDL are less than 500mV, Vref may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Symbol
Parameter
Rating
Units
Notes
TOPER
Operating Temperature
0 to 85 (Standard Grade)
℃
1, 2
Note:
1. Operating temperature is the case surface temperature on the center/top side of the DRAM.
2. The operation temperature range is the temperature where all DRAM specification will be supported. Outside of this temperature range, even if it is still within the limit
of stress condition, some deviation on portion of operation specification may be required. During operation, the DRAM case temperature must be maintained between 0
℃
-85 ℃ under all other specification parameter. However, in some applications, it is desirable to operate the DRAM up to 95 ℃ case temperature. Therefore, two
spec. may exist.
Supporting 0℃-85℃ with full JEDEC AC & DC spec. This is the minimum requirements for all operating temperature options.
This is an optional feature and not required. Supporting 0℃-85℃ and being able to extend to 95℃ with doubling auto-refresh command in frequency to a 32ms
period (tRFI=3.9μs)
Currently the period Self-Refresh interval is hard coded within the DRAM to a vendor specific value. There is a migration plan to support higher temperature
Self-Refresh entry via the control of EMRS (2) bit A7.