參數(shù)資料
型號: NT5TU64M16DG-3C
廠商: NANYA TECHNOLOGY CORP
元件分類: DRAM
英文描述: 64M X 16 DDR DRAM, 0.45 ns, PBGA84
封裝: GREEN, BGA-84
文件頁數(shù): 48/85頁
文件大?。?/td> 2622K
代理商: NT5TU64M16DG-3C
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
52
REV 1.0
06 / 2010
Asynchronous CKE Low Event
DRAM requires CKE to be maintained “high” for all valid operations as defined in this data sheet. If CKE asynchronously
drops “l(fā)ow” during any valid operation DRAM is not guaranteed to preserve the contents of the memory array. If this event
occurs, the memory controller must satisfy a time delay ( tdelay ) before turning off the clocks. Stable clocks must exist at the
input of DRAM before CKE is raised “high” again. The DRAM must be fully re-initialized as described the the initialization
sequence (section 2.2.1, step 4 thru 13). DRAM is ready for normal operation after the initialization sequence. See AC
timing parametric table for tdelay specification.
Asynchronous CKE Low Event
CKE
CKE drops low due to an
asynchronous reset event
Clocks can be turned off after
this point
tdelay
CK, CK
stable clocks
相關(guān)PDF資料
PDF描述
NTA2425E
NTA2425F
NTA2410-10
NTD2410F
NTA2425-10
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
NT5TU64M16GG-AC 制造商:Nanya Technology Corporation 功能描述:DRAM
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NT5TU64M16HG-AC 制造商:Nanya Technology Corporation 功能描述:MEMORY IC
NT5TU64M16HG-BE 制造商:Nanya Technology Corporation 功能描述:MEMORY IC
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