![](http://datasheet.mmic.net.cn/180000/NT5TU64M16DG-3C_datasheet_11338978/NT5TU64M16DG-3C_53.png)
NT5TU256M4GE / NT5TU128M8GE / NT5TU64M16GG
1Gb DDR2 SDRAM
53
REV 1.0
06 / 2010
Truth Table
Command Truth Table
Function
CKE
CS
RAS
CAS
WE
BA0-BA2 A13-A11 A10
A9 - A0
Notes
Previous
Cycle
Current
Cycle
(Extended) Mode Register Set
H
L
BA
OP Code
1, 2
Auto-Refresh
H
L
H
X
1
Self-Refresh Entry
H
L
H
X
1,8
Self-Refresh Exit
L
H
X
1,7,8
Single Bank Precharge
H
L
H
L
BA
X
L
X
1,2
Precharge all Banks
H
L
H
L
X
H
X
1
Bank Activate
H
L
H
BA
Row Address
1,2
Write
H
L
H
L
BA
Column
L
Column
1,2,3
Write with Auto-Precharge
H
L
H
L
BA
Column
H
Column
1,2,3
Read
H
L
H
L
H
BA
Column
L
Column
1,2,3
Read with Auto-Precharge
H
L
H
L
H
BA
Column
H
Column
1,2,3
No Operation
H
X
L
H
X
1
Device Deselect
H
X
H
X
1
Power Down Entry
H
L
H
X
1,4
L
H
Power Down Exit
L
H
X
1,4
L
H
1. All DDR2 SDRAM commands are defined by states of , , , , and CKE at the rising edge of the clock.
2. Bank addresses (BAx) determine which bank is to be operated upon. For (E) MRS BAx selects an (Extended) Mode Register.
3. Burst reads or writes at BL = 4 cannot be terminated. See sections "Reads interrupted by a Read" and "Writes interrupted by a Write" inspection for details.
4. The Power Down Mode does not perform any refresh operations. The duration of Power Down is therefore limited by the refresh requirements outlined.
5. The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
6. X means "H or L (but a defined logic level)".
7. Self refresh exit is asynchronous.
8. Vref must be maintained during Self Refresh operation.